From: Alex Solomatnikov <sols@sifive.com>
Date: Thu, 9 Feb 2017 19:36:19 +0000 (-0800)
Subject: Made regs 32-bit word aligned to match the rest of the system
X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=commitdiff_plain;h=72e4b60d81e5ae1cbc518c9a3bda486a56dfca8c

Made regs 32-bit word aligned to match the rest of the system
---

diff --git a/src/main/scala/devices/i2c/I2CCtrlRegs.scala b/src/main/scala/devices/i2c/I2CCtrlRegs.scala
index 1a69783..aaa6197 100644
--- a/src/main/scala/devices/i2c/I2CCtrlRegs.scala
+++ b/src/main/scala/devices/i2c/I2CCtrlRegs.scala
@@ -6,8 +6,8 @@ package sifive.blocks.devices.i2c
 
 object I2CCtrlRegs {
   val prescaler_lo = 0x00  // low byte clock prescaler register
-  val prescaler_hi = 0x01  // high byte clock prescaler register
-  val control      = 0x02  // control register
-  val data         = 0x03  // write: transmit byte, read: receive byte
-  val cmd_status   = 0x04  // write: command, read: status
+  val prescaler_hi = 0x04  // high byte clock prescaler register
+  val control      = 0x08  // control register
+  val data         = 0x0c  // write: transmit byte, read: receive byte
+  val cmd_status   = 0x10  // write: command, read: status
 }