From: Wesley W. Terpstra <wesley@sifive.com>
Date: Sat, 4 Feb 2017 02:17:58 +0000 (-0800)
Subject: xilinx mig: track changes in rocket-chip
X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=commitdiff_plain;h=88e4c8ee2083559c68c01cc4ea8340b4dfd03d54

xilinx mig: track changes in rocket-chip
---

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
index b52b37c..4586949 100644
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
@@ -11,7 +11,7 @@ trait PeripheryXilinxVC707MIG extends TopNetwork {
 
   val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
   require(p(BankedL2Config).nMemoryChannels == 1, "Coreplex must have 1 master memory port")
-  val mem = Seq(xilinxvc707mig.node)
+  xilinxvc707mig.node := mem(0).node
 }
 
 trait PeripheryXilinxVC707MIGBundle extends TopNetworkBundle {