From 38f537c438224418356c1ef6979c482841a0da4c Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Wed, 20 Sep 2017 16:43:42 -0700 Subject: [PATCH] device pins: Create classes that can be something other than a Pin subclass --- src/main/scala/devices/i2c/I2CPins.scala | 7 +++- src/main/scala/devices/pwm/PWMPeriphery.scala | 9 ++++- .../scala/devices/uart/UARTPeriphery.scala | 19 ----------- src/main/scala/devices/uart/UARTPins.scala | 33 +++++++++++++++++++ 4 files changed, 47 insertions(+), 21 deletions(-) create mode 100644 src/main/scala/devices/uart/UARTPins.scala diff --git a/src/main/scala/devices/i2c/I2CPins.scala b/src/main/scala/devices/i2c/I2CPins.scala index 6bf40ae..6ad1783 100644 --- a/src/main/scala/devices/i2c/I2CPins.scala +++ b/src/main/scala/devices/i2c/I2CPins.scala @@ -6,13 +6,18 @@ import chisel3.experimental.{withClockAndReset} import freechips.rocketchip.util.SyncResetSynchronizerShiftReg import sifive.blocks.devices.pinctrl.{Pin, PinCtrl} -class I2CPins[T <: Pin](pingen: () => T) extends Bundle { +class I2CSignals[T <: Data](pingen: () => T) extends Bundle { val scl: T = pingen() val sda: T = pingen() override def cloneType: this.type = this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type] +} + +class I2CPins[T <: Pin](pingen: () => T) extends I2CSignals[T](pingen) { + override def cloneType: this.type = + this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type] def fromPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = { withClockAndReset(clock, reset) { diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala index 3754f71..94f65dd 100644 --- a/src/main/scala/devices/pwm/PWMPeriphery.scala +++ b/src/main/scala/devices/pwm/PWMPeriphery.scala @@ -13,10 +13,17 @@ class PWMPortIO(val c: PWMParams) extends Bundle { override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type] } -class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends Bundle { +class PWMSignals[T <: Data] (pingen: ()=> T, val c: PWMParams) extends Bundle { val pwm: Vec[T] = Vec(c.ncmp, pingen()) + override def cloneType: this.type = + this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type] +} + + +class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends PWMSignals[T](pingen, c) { + override def cloneType: this.type = this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type] diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala index de4392c..95d0c3b 100644 --- a/src/main/scala/devices/uart/UARTPeriphery.scala +++ b/src/main/scala/devices/uart/UARTPeriphery.scala @@ -4,10 +4,8 @@ package sifive.blocks.devices.uart import Chisel._ import chisel3.experimental.{withClockAndReset} import freechips.rocketchip.config.Field -import freechips.rocketchip.util.SyncResetSynchronizerShiftReg import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus} import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} -import sifive.blocks.devices.pinctrl.{Pin} case object PeripheryUARTKey extends Field[Seq[UARTParams]] @@ -39,20 +37,3 @@ trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUA io <> device.module.io.port } } - -class UARTPins[T <: Pin] (pingen: () => T) extends Bundle { - val rxd = pingen() - val txd = pingen() - - override def cloneType: this.type = - this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type] - - def fromPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) { - withClockAndReset(clock, reset) { - txd.outputPin(uart.txd) - val rxd_t = rxd.inputPin() - uart.rxd := SyncResetSynchronizerShiftReg(rxd_t, syncStages, init = Bool(true), name = Some("uart_rxd_sync")) - } - } -} - diff --git a/src/main/scala/devices/uart/UARTPins.scala b/src/main/scala/devices/uart/UARTPins.scala new file mode 100644 index 0000000..a5885a2 --- /dev/null +++ b/src/main/scala/devices/uart/UARTPins.scala @@ -0,0 +1,33 @@ +// See LICENSE for license details. +package sifive.blocks.devices.uart + +import Chisel._ +import chisel3.experimental.{withClockAndReset} +import freechips.rocketchip.config.Field +import freechips.rocketchip.util.SyncResetSynchronizerShiftReg +import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus} +import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} +import sifive.blocks.devices.pinctrl.{Pin} + + +class UARTSignals[T <: Data] (pingen: () => T) extends Bundle { + val rxd = pingen() + val txd = pingen() + + override def cloneType: this.type = + this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type] +} + +class UARTPins[T <: Pin] (pingen: () => T) extends UARTSignals[T](pingen, c) { + override def cloneType: this.type = + this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type] + + def fromPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) { + withClockAndReset(clock, reset) { + txd.outputPin(uart.txd) + val rxd_t = rxd.inputPin() + uart.rxd := SyncResetSynchronizerShiftReg(rxd_t, syncStages, init = Bool(true), name = Some("uart_rxd_sync")) + } + } +} + -- 2.30.2