From d61d86e08417ae182e7f2e8aabebc193941ce31a Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 20 Jan 2017 22:38:27 -0800 Subject: [PATCH] xilinx pcie: put buffers before the outputs to the controller --- .../scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala index bd3b1ef..b82186c 100644 --- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala +++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala @@ -26,8 +26,8 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule { val intnode = IntSourceNode(1) val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1) - axi_to_pcie_x1.slave := TLToAXI4(idBits=4)(slave) - axi_to_pcie_x1.control := AXI4Fragmenter(lite=true, maxInFlight=4)(TLToAXI4(idBits=0)(control)) + axi_to_pcie_x1.slave := AXI4Buffer()(TLToAXI4(idBits=4)(slave)) + axi_to_pcie_x1.control := AXI4Buffer()(AXI4Fragmenter(lite=true, maxInFlight=4)(TLToAXI4(idBits=0)(control))) master := TLWidthWidget(8)(AXI4ToTL()(AXI4Fragmenter()(axi_to_pcie_x1.master))) lazy val module = new LazyModuleImp(this) { -- 2.30.2