super is a keyword: replace with "supermode" in TLB and PermValidator

[soc.git] / TLB / src / TLB.py

diff --git a/TLB/src/TLB.py b/TLB/src/TLB.py
index 58379586f24849d1bb50a77afd55d46ca289aecc..c1e8815e69d989d176ecd0d1f987bfdb0e9d4adf 100644 (file)
--- a/TLB/src/TLB.py
+++ b/TLB/src/TLB.py
@@ -1,13 +1,16 @@
+""" TLB Module
+
+    The expected form of the data is:
+    * Item (Bits)
+    * Tag (N - 79) / ASID (78 - 64) / PTE (63 - 0)
+"""
+
 from nmigen import Memory, Module, Signal
 from nmigen.cli import main
 
 from PermissionValidator import PermissionValidator
 from Cam import Cam
 
-# The expected form of the data is
-# Item (Bits)
-# Tag (N - 79) / ASID (78 - 64) / PTE (63 - 0)
-
 class TLB():
     def __init__(self, asid_size, vma_size, pte_size):
         """ Arguments
@@ -32,7 +35,7 @@ class TLB():
         self.perm_validator = PermissionValidator(asid_size + pte_size)
 
         # Inputs
-        self.super = Signal(1) # Supervisor Mode
+        self.supermode = Signal(1) # Supervisor Mode
         self.super_access = Signal(1) # Supervisor Access
         self.command = Signal(2) # 00=None, 01=Search, 10=Write L1, 11=Write L2
         self.xwr = Signal(3) # Execute, Write, Read
@@ -106,7 +109,7 @@ class TLB():
                         # Execute, Read, Write
                         self.perm_validator.xwr.eq(self.xwr),
                         # Supervisor Mode
-                        self.perm_validator.super.eq(self.super),
+                        self.perm_validator.supermode.eq(self.supermode),
                         # Supverisor Access
                         self.perm_validator.super_access.eq(self.super_access),
                         # Address Space IDentifier (ASID)