experiment switching over fwd and rsel in dependency cell

[soc.git] / src / scoreboard / dependence_cell.py

diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py
index d386852e2cb108f1df6d2408bdd2f27b0d0ceb35..1ae81b59a11c12668403d5d672f70322c954560b 100644 (file)
--- a/src/scoreboard/dependence_cell.py
+++ b/src/scoreboard/dependence_cell.py
@@ -89,14 +89,14 @@ class DependenceCell(Elaboratable):
         m.d.comb += src2_l.r.eq(self.go_rd_i)
 
         # FU "Forward Progress" (read out horizontally)
-        m.d.comb += self.dest_fwd_o.eq(dest_l.q & self.go_wr_i)
-        m.d.comb += self.src1_fwd_o.eq(src1_l.q & self.go_rd_i)
-        m.d.comb += self.src2_fwd_o.eq(src2_l.q & self.go_rd_i)
+        m.d.comb += self.dest_fwd_o.eq(dest_l.q & self.dest_i)
+        m.d.comb += self.src1_fwd_o.eq(src1_l.q & self.src1_i)
+        m.d.comb += self.src2_fwd_o.eq(src2_l.q & self.src2_i)
 
         # Register File Select (read out vertically)
-        m.d.sync += self.dest_rsel_o.eq(dest_l.q & self.dest_i)
-        m.d.sync += self.src1_rsel_o.eq(src1_l.q & self.src1_i)
-        m.d.sync += self.src2_rsel_o.eq(src2_l.q & self.src2_i)
+        m.d.sync += self.dest_rsel_o.eq(dest_l.q & ~self.go_wr_i)
+        m.d.sync += self.src1_rsel_o.eq(src1_l.q & ~self.go_rd_i)
+        m.d.sync += self.src2_rsel_o.eq(src2_l.q & ~self.go_rd_i)
 
         return m