from nmigen.compat.sim import run_simulation
from nmigen.cli import verilog, rtlil
-from nmigen import Module, Signal, Elaboratable
+from nmigen import Module, Signal, Elaboratable, Array, Cat
from nmutil.latch import SRLatch
+class DepCell(Elaboratable):
+ """ implements 11.4.7 mitch alsup dependence cell, p27
+ adjusted to be clock-sync'd on rising edge only.
+ mitch design (as does 6600) requires alternating rising/falling clock
+ """
+ def __init__(self):
+ # inputs
+ self.reg_i = Signal(reset_less=True) # reg bit in (top)
+ self.issue_i = Signal(reset_less=True) # Issue in (top)
+ self.go_i = Signal(reset_less=True) # Go read/write in (left)
+
+ # for Register File Select Lines (vertical)
+ self.rsel_o = Signal(reset_less=True) # reg sel (bottom)
+ # for Function Unit "forward progress" (horizontal)
+ self.fwd_o = Signal(reset_less=True) # FU forard progress (right)
+
+ def elaborate(self, platform):
+ m = Module()
+ m.submodules.l = l = SRLatch(sync=False) # async latch
+
+ # record current version of q in a sync'd register
+ cq = Signal() # resets to 0
+ m.d.sync += cq.eq(l.q)
+
+ # reset on go HI, set on dest and issue
+ m.d.comb += l.s.eq(self.issue_i & self.reg_i)
+ m.d.comb += l.r.eq(self.go_i)
+
+ # Function Unit "Forward Progress".
+ m.d.comb += self.fwd_o.eq((cq | l.q) & self.reg_i & ~self.issue_i)
+
+ # Register Select. Activated on go read/write and *current* latch set
+ m.d.comb += self.rsel_o.eq((cq | l.q) & self.go_i)
+
+ return m
+
+ def __iter__(self):
+ yield self.regt_i
+ yield self.issue_i
+ yield self.go_i
+ yield self.rsel_o
+ yield self.fwd_o
+
+ def ports(self):
+ return list(self)
+
+
class DependenceCell(Elaboratable):
""" implements 11.4.7 mitch alsup dependence cell, p27
"""
self.src2_i = Signal(reset_less=True) # oper2 in (top)
self.issue_i = Signal(reset_less=True) # Issue in (top)
- self.go_write_i = Signal(reset_less=True) # Go Write in (left)
- self.go_read_i = Signal(reset_less=True) # Go Read in (left)
+ self.go_wr_i = Signal(reset_less=True) # Go Write in (left)
+ self.go_rd_i = Signal(reset_less=True) # Go Read in (left)
# for Register File Select Lines (vertical)
self.dest_rsel_o = Signal(reset_less=True) # dest reg sel (bottom)
def elaborate(self, platform):
m = Module()
- m.submodules.dest_l = dest_l = SRLatch()
- m.submodules.src1_l = src1_l = SRLatch()
- m.submodules.src2_l = src2_l = SRLatch()
+ m.submodules.dest_c = dest_c = DepCell()
+ m.submodules.src1_c = src1_c = DepCell()
+ m.submodules.src2_c = src2_c = DepCell()
- # destination latch: reset on go_write HI, set on dest and issue
- m.d.comb += dest_l.s.eq(self.issue_i & self.dest_i)
- m.d.comb += dest_l.r.eq(self.go_write_i)
+ # connect issue
+ for c in [dest_c, src1_c, src2_c]:
+ m.d.comb += c.issue_i.eq(self.issue_i)
- # src1 latch: reset on go_read HI, set on src1_i and issue
- m.d.comb += src1_l.s.eq(self.issue_i & self.src1_i)
- m.d.comb += src1_l.r.eq(self.go_read_i)
+ # connect go_rd / go_wr (dest->wr, src->rd)
+ m.d.comb += dest_c.go_i.eq(self.go_wr_i)
+ m.d.comb += src1_c.go_i.eq(self.go_rd_i)
+ m.d.comb += src2_c.go_i.eq(self.go_rd_i)
- # src2 latch: reset on go_read HI, set on op2_i and issue
- m.d.comb += src2_l.s.eq(self.issue_i & self.src2_i)
- m.d.comb += src2_l.r.eq(self.go_read_i)
+ # connect input reg bit (unary)
+ for c, reg in [(dest_c, self.dest_i),
+ (src1_c, self.src1_i),
+ (src2_c, self.src2_i)]:
+ m.d.comb += c.reg_i.eq(reg)
- # FU "Forward Progress" (read out horizontally)
- m.d.comb += self.dest_fwd_o.eq(dest_l.qn & self.dest_i)
- m.d.comb += self.src1_fwd_o.eq(src1_l.qn & self.src1_i)
- m.d.comb += self.src2_fwd_o.eq(src2_l.qn & self.src2_i)
+ # connect fwd / reg-sel outputs
+ for c, fwd, rsel in [(dest_c, self.dest_fwd_o, self.dest_rsel_o),
+ (src1_c, self.src1_fwd_o, self.src1_rsel_o),
+ (src2_c, self.src2_fwd_o, self.src2_rsel_o)]:
+ m.d.comb += fwd.eq(c.fwd_o)
+ m.d.comb += rsel.eq(c.rsel_o)
- # Register File Select (read out vertically)
- m.d.comb += self.dest_rsel_o.eq(dest_l.qn & self.go_write_i)
- m.d.comb += self.src1_rsel_o.eq(src1_l.qn & self.go_read_i)
- m.d.comb += self.src2_rsel_o.eq(src2_l.qn & self.go_read_i)
+ return m
+
+ def __iter__(self):
+ yield self.dest_i
+ yield self.src1_i
+ yield self.src2_i
+ yield self.issue_i
+ yield self.go_wr_i
+ yield self.go_rd_i
+ yield self.dest_rsel_o
+ yield self.src1_rsel_o
+ yield self.src2_rsel_o
+ yield self.dest_fwd_o
+ yield self.src1_fwd_o
+ yield self.src2_fwd_o
+
+ def ports(self):
+ return list(self)
+
+
+class DependencyRow(Elaboratable):
+ def __init__(self, n_reg_col):
+ self.n_reg_col = n_reg_col
+
+ # ----
+ # fields all match DependencyCell precisely
+
+ self.dest_i = Signal(n_reg_col, reset_less=True)
+ self.src1_i = Signal(n_reg_col, reset_less=True)
+ self.src2_i = Signal(n_reg_col, reset_less=True)
+
+ self.issue_i = Signal(reset_less=True)
+ self.go_wr_i = Signal(reset_less=True)
+ self.go_rd_i = Signal(reset_less=True)
+
+ self.dest_rsel_o = Signal(n_reg_col, reset_less=True)
+ self.src1_rsel_o = Signal(n_reg_col, reset_less=True)
+ self.src2_rsel_o = Signal(n_reg_col, reset_less=True)
+
+ self.dest_fwd_o = Signal(n_reg_col, reset_less=True)
+ self.src1_fwd_o = Signal(n_reg_col, reset_less=True)
+ self.src2_fwd_o = Signal(n_reg_col, reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+ rcell = Array(DependenceCell() for f in range(self.n_reg_col))
+ for rn in range(self.n_reg_col):
+ setattr(m.submodules, "dm_r%d" % rn, rcell[rn])
+
+ # ---
+ # connect Dep dest/src to module dest/src
+ # ---
+ dest_i = []
+ src1_i = []
+ src2_i = []
+ for rn in range(self.n_reg_col):
+ dc = rcell[rn]
+ # accumulate cell inputs dest/src1/src2
+ dest_i.append(dc.dest_i)
+ src1_i.append(dc.src1_i)
+ src2_i.append(dc.src2_i)
+ # wire up inputs from module to row cell inputs (Cat is gooood)
+ m.d.comb += [Cat(*dest_i).eq(self.dest_i),
+ Cat(*src1_i).eq(self.src1_i),
+ Cat(*src2_i).eq(self.src2_i),
+ ]
+
+ # ---
+ # connect Dep issue_i/go_rd_i/go_wr_i to module issue_i/go_rd/go_wr
+ # ---
+ for rn in range(self.n_reg_col):
+ dc = rcell[rn]
+ m.d.comb += [dc.go_rd_i.eq(self.go_rd_i),
+ dc.go_wr_i.eq(self.go_wr_i),
+ dc.issue_i.eq(self.issue_i),
+ ]
+
+ # ---
+ # connect Function Unit vector
+ # ---
+ dest_fwd_o = []
+ src1_fwd_o = []
+ src2_fwd_o = []
+ for rn in range(self.n_reg_col):
+ dc = rcell[rn]
+ # accumulate cell fwd outputs for dest/src1/src2
+ dest_fwd_o.append(dc.dest_fwd_o)
+ src1_fwd_o.append(dc.src1_fwd_o)
+ src2_fwd_o.append(dc.src2_fwd_o)
+ # connect cell fwd outputs to FU Vector Out [Cat is gooood]
+ m.d.comb += [self.dest_fwd_o.eq(Cat(*dest_fwd_o)),
+ self.src1_fwd_o.eq(Cat(*src1_fwd_o)),
+ self.src2_fwd_o.eq(Cat(*src2_fwd_o))
+ ]
+
+ # ---
+ # connect Reg Selection vector
+ # ---
+ dest_rsel_o = []
+ src1_rsel_o = []
+ src2_rsel_o = []
+ for rn in range(self.n_reg_col):
+ dc = rcell[rn]
+ # accumulate cell reg-select outputs dest/src1/src2
+ dest_rsel_o.append(dc.dest_rsel_o)
+ src1_rsel_o.append(dc.src1_rsel_o)
+ src2_rsel_o.append(dc.src2_rsel_o)
+ # connect cell reg-select outputs to Reg Vector Out
+ m.d.comb += self.dest_rsel_o.eq(Cat(*dest_rsel_o))
+ m.d.comb += self.src1_rsel_o.eq(Cat(*src1_rsel_o))
+ m.d.comb += self.src2_rsel_o.eq(Cat(*src2_rsel_o))
return m
yield self.src1_i
yield self.src2_i
yield self.issue_i
- yield self.go_write_i
- yield self.go_read_i
+ yield self.go_wr_i
+ yield self.go_rd_i
yield self.dest_rsel_o
yield self.src1_rsel_o
yield self.src2_rsel_o
yield self.dest_fwd_o
yield self.src1_fwd_o
yield self.src2_fwd_o
-
+
def ports(self):
return list(self)
yield
yield dut.issue_i.eq(0)
yield
- yield dut.go_read_i.eq(1)
+ yield dut.go_rd_i.eq(1)
yield
- yield dut.go_read_i.eq(0)
+ yield dut.go_rd_i.eq(0)
yield
- yield dut.go_write_i.eq(1)
+ yield dut.go_wr_i.eq(1)
yield
- yield dut.go_write_i.eq(0)
+ yield dut.go_wr_i.eq(0)
yield
def test_dcell():
+ dut = DependencyRow(4)
+ vl = rtlil.convert(dut, ports=dut.ports())
+ with open("test_drow.il", "w") as f:
+ f.write(vl)
+
dut = DependenceCell()
vl = rtlil.convert(dut, ports=dut.ports())
with open("test_dcell.il", "w") as f:
projects / soc.git / blobdiff