clear out DEC in core.cur_state.dec due to spurious interrupt.

[soc.git] / src / soc / fu / spr / pipe_data.py

diff --git a/src/soc/fu/spr/pipe_data.py b/src/soc/fu/spr/pipe_data.py
index 5cc7835e6c0e7c432ac4fc98abb943d530a05827..21db95827ccc53d3f5d67454ef13f5881aff7d51 100644 (file)
--- a/src/soc/fu/spr/pipe_data.py
+++ b/src/soc/fu/spr/pipe_data.py
@@ -28,6 +28,10 @@ class SPRInputData(FUBaseData):
         # convenience
         self.a = self.ra
 
+# note that state1 gets a corresponding "state1" write port created
+# by core.py which is "monitored" by TestIssuerBase (hack-job, sigh).
+# when writes are spotted then the DEC/TB FSM resets and re-reads
+# DEC/TB.
 
 class SPROutputData(FUBaseData):
     regspec = [('INT', 'o', '0:63'),        # RT