X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=blobdiff_plain;f=TLB%2Fsrc%2FPermissionValidator.py;h=0808ab256c5e654419d494aa6929e63406e164f8;hp=6e8bee894ca661043954b79fe7225ec333e7ffc3;hb=382f1564ab31cd82ec9f1125b260205e21d30df0;hpb=b4ff36102d5ffbb29c6740270ca4a59a8c50895b

diff --git a/TLB/src/PermissionValidator.py b/TLB/src/PermissionValidator.py
index 6e8bee89..0808ab25 100644
--- a/TLB/src/PermissionValidator.py
+++ b/TLB/src/PermissionValidator.py
@@ -20,7 +20,7 @@ class PermissionValidator():
         # Input
         self.data = Signal(data_size);
         self.xwr = Signal(3) # Execute, Write, Read
-        self.super = Signal(1) # Supervisor Mode
+        self.supermode = Signal(1) # Supervisor Mode
         self.super_access = Signal(1) # Supervisor Access
         self.asid = Signal(15) # Address Space IDentifier (ASID)
 
@@ -36,7 +36,7 @@ class PermissionValidator():
                       & data[2] == self.xwr[1] \
                       & data[1] == self.xwr[0]):
                 # Supervisor Logic
-                with m.If(self.super):
+                with m.If(self.supermode):
                     # Valid if entry is not in user mode or supervisor
                     # has Supervisor User Memory (SUM) access via the
                     # SUM bit in the sstatus register
@@ -48,4 +48,4 @@ class PermissionValidator():
             with m.Else():
                 m.comb += self.valid.eq(0)
         with m.Else():
-            m.comb += self.valid.eq(0)
\ No newline at end of file
+            m.comb += self.valid.eq(0)