scoreboard 6600 experimentation

diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py
index d03a8d2cbfdf342065b8d71b508e2bbdc1c18178..b4df27e5181a9193599ef4bd3cc834bba5eee5cb 100644 (file)
--- a/src/experiment/compalu.py
+++ b/src/experiment/compalu.py
@@ -54,7 +54,7 @@ class ComputationUnitNoDelay(Elaboratable):
         m.d.comb += self.busy_o.eq(opc_l.q) # busy out
 
         with m.If(req_l.qn & opc_l.q & (self.counter == 0)):
-            m.d.sync += self.counter.eq(3)
+            m.d.sync += self.counter.eq(5)
         with m.If(self.counter > 0):
             m.d.sync += self.counter.eq(self.counter - 1)
         with m.If((self.counter == 1) | (self.counter == 0)):

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index 99111b9c103ae6d7a3b66bbcde3e56b08c38eee4..6637d280b30e4da1f8a39f1e1b098cd195903754 100644 (file)
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -119,15 +119,15 @@ class FunctionUnits(Elaboratable):
         intregdeps = FURegDepMatrix(n_int_fus, self.n_regs)
         m.submodules.intregdeps = intregdeps
 
-        m.d.sync += self.g_int_rd_pend_o.eq(intregdeps.rd_pend_o)
-        m.d.sync += self.g_int_wr_pend_o.eq(intregdeps.wr_pend_o)
+        m.d.comb += self.g_int_rd_pend_o.eq(intregdeps.rd_pend_o)
+        m.d.comb += self.g_int_wr_pend_o.eq(intregdeps.wr_pend_o)
 
-        m.d.sync += intfudeps.rd_pend_i.eq(self.g_int_rd_pend_o)
-        m.d.sync += intfudeps.wr_pend_i.eq(self.g_int_wr_pend_o)
+        m.d.comb += intfudeps.rd_pend_i.eq(self.g_int_rd_pend_o)
+        m.d.comb += intfudeps.wr_pend_i.eq(self.g_int_wr_pend_o)
 
-        m.d.sync += intfudeps.issue_i.eq(self.fn_issue_i)
-        m.d.sync += intfudeps.go_rd_i.eq(self.go_rd_i)
-        m.d.sync += intfudeps.go_wr_i.eq(self.go_wr_i)
+        m.d.comb += intfudeps.issue_i.eq(self.fn_issue_i)
+        m.d.comb += intfudeps.go_rd_i.eq(self.go_rd_i)
+        m.d.comb += intfudeps.go_wr_i.eq(self.go_wr_i)
         m.d.comb += self.readable_o.eq(intfudeps.readable_o)
         m.d.comb += self.writable_o.eq(intfudeps.writable_o)
 
@@ -253,7 +253,8 @@ class Scoreboard(Elaboratable):
 
         # Connect Picker
         #---------
-        m.d.comb += intpick1.go_rd_i[0:2].eq(~go_rd_i[0:2])
+        #m.d.comb += intpick1.go_rd_i[0:2].eq(~go_rd_i[0:2])
+        m.d.comb += intpick1.go_rd_i[0:2].eq(cu.req_rel_o[0:2])
         m.d.comb += intpick1.req_rel_i[0:2].eq(cu.req_rel_o[0:2])
         int_readable_o = intfus.readable_o
         int_writable_o = intfus.writable_o
@@ -357,8 +358,8 @@ def scoreboard_sim(dut, alusim):
     yield dut.int_store_i.eq(0)
 
     for i in range(1, dut.n_regs):
-        yield dut.intregs.regs[i].reg.eq(i*2)
-        alusim.setval(i, i*2)
+        yield dut.intregs.regs[i].reg.eq(4+i*2)
+        alusim.setval(i, 4+i*2)
 
     yield
 
@@ -386,7 +387,7 @@ def scoreboard_sim(dut, alusim):
         instrs.append((5, 3, 3, 1))
 
     if True:
-        instrs.append((7, 2, 6, 1))
+        instrs.append((1, 1, 2, 0))
         instrs.append((3, 7, 1, 1))
         #instrs.append((2, 2, 3, 1))
 
@@ -432,8 +433,8 @@ def explore_groups(dut):
 
 
 def test_scoreboard():
-    dut = Scoreboard(32, 8)
-    alusim = RegSim(32, 8)
+    dut = Scoreboard(16, 8)
+    alusim = RegSim(16, 8)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_scoreboard6600.il", "w") as f:
         f.write(vl)

diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py
index 0b9ebd922c221555faedc63afe04ef148ba22733..6c779a358b8ec4bb7b1f4ffc88cdfc135c2665c5 100644 (file)
--- a/src/scoreboard/dependence_cell.py
+++ b/src/scoreboard/dependence_cell.py
@@ -51,9 +51,9 @@ class DependenceCell(Elaboratable):
         m.d.comb += self.src2_fwd_o.eq(src2_l.q & self.go_rd_i)
 
         # Register File Select (read out vertically)
-        m.d.comb += self.dest_rsel_o.eq(dest_l.q & self.dest_i)
-        m.d.comb += self.src1_rsel_o.eq(src1_l.q & self.src1_i)
-        m.d.comb += self.src2_rsel_o.eq(src2_l.q & self.src2_i)
+        m.d.sync += self.dest_rsel_o.eq(dest_l.q & self.dest_i)
+        m.d.sync += self.src1_rsel_o.eq(src1_l.q & self.src1_i)
+        m.d.sync += self.src2_rsel_o.eq(src2_l.q & self.src2_i)
 
         return m
 

diff --git a/src/scoreboard/fu_picker_vec.py b/src/scoreboard/fu_picker_vec.py
index 21ed7fc2ddf0d015b34956a806ec3d4e41b90cda..fd44c45ff5a95db3e1a66cb6a5903f47704d0b01 100644 (file)
--- a/src/scoreboard/fu_picker_vec.py
+++ b/src/scoreboard/fu_picker_vec.py
@@ -16,6 +16,6 @@ class FU_Pick_Vec(Elaboratable):
     def elaborate(self, platform):
         m = Module()
         m.d.comb += self.readable_o.eq(self.rd_pend_i.bool())
-        m.d.comb += self.writable_o.eq(~self.wr_pend_i.bool())
+        m.d.comb += self.writable_o.eq(self.wr_pend_i.bool())
         return m
 

diff --git a/src/scoreboard/fu_reg_matrix.py b/src/scoreboard/fu_reg_matrix.py
index 1e74ee436bed7ef0ffbc6a9f32168d6e6bc01923..b8b657e402fb02e1b66f53b0abffafd13aed9816 100644 (file)
--- a/src/scoreboard/fu_reg_matrix.py
+++ b/src/scoreboard/fu_reg_matrix.py
@@ -119,10 +119,19 @@ class FURegDepMatrix(Elaboratable):
         src2_rsel = []
         for rn in range(self.n_reg_col):
             rsv = regrsv[rn]
+            dest_rsel_o = []
+            src1_rsel_o = []
+            src2_rsel_o = []
+            for fu in range(self.n_fu_row):
+                dc = dm[fu]
+                # accumulate cell reg-select outputs dest/src1/src2
+                dest_rsel_o.append(dc.dest_rsel_o[rn])
+                src1_rsel_o.append(dc.src1_rsel_o[rn])
+                src2_rsel_o.append(dc.src2_rsel_o[rn])
             # connect cell reg-select outputs to Reg Vector In
-            m.d.comb += [rsv.dest_rsel_i.eq(dc.dest_rsel_o),
-                         rsv.src1_rsel_i.eq(dc.src1_rsel_o),
-                         rsv.src2_rsel_i.eq(dc.src2_rsel_o),
+            m.d.comb += [rsv.dest_rsel_i.eq(Cat(*dest_rsel_o)),
+                         rsv.src1_rsel_i.eq(Cat(*src1_rsel_o)),
+                         rsv.src2_rsel_i.eq(Cat(*src2_rsel_o)),
                         ]
             # accumulate Reg-Sel Vector outputs
             dest_rsel.append(rsv.dest_rsel_o)

diff --git a/src/scoreboard/group_picker.py b/src/scoreboard/group_picker.py
index 5a865640cb93f8bf400f32f963a594cb48042704..e5fad2499151a1be18370b2b644f9cea3c8bc2a3 100644 (file)
--- a/src/scoreboard/group_picker.py
+++ b/src/scoreboard/group_picker.py
@@ -10,7 +10,7 @@ class PriorityPicker(Elaboratable):
         self.wid = wid
         # inputs
         self.i = Signal(wid, reset_less=True)
-        self.o = Signal(wid, reset_less=True) 
+        self.o = Signal(wid, reset_less=True)
 
     def elaborate(self, platform):
         m = Module()
@@ -25,7 +25,7 @@ class PriorityPicker(Elaboratable):
                 m.d.comb += t.eq(self.i[i])
             else:
                 m.d.comb += t.eq(~Cat(ni[i], *self.i[:i]).bool())
-        
+
         # we like Cat(*xxx).  turn lists into concatenated bits
         m.d.comb += self.o.eq(Cat(*res))
 
@@ -34,7 +34,7 @@ class PriorityPicker(Elaboratable):
     def __iter__(self):
         yield self.i
         yield self.o
-                
+ 
     def ports(self):
         return list(self)
 
@@ -75,7 +75,7 @@ class GroupPicker(Elaboratable):
         yield self.req_rel_i
         yield self.go_rd_o
         yield self.go_wr_o
-                
+
     def ports(self):
         return list(self)