From: Luke Kenneth Casson Leighton Date: Sun, 19 May 2019 06:15:39 +0000 (+0100) Subject: experiment switching over fwd and rsel in dependency cell X-Git-Tag: div_pipeline~2015 X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=commitdiff_plain;h=e79992af9cba2cb73b0efcf6478a83e52c757ec6;hp=42ff5cc0d2fa4aaf0f2cef99735cb9e56e3479c8 experiment switching over fwd and rsel in dependency cell --- diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py index d386852e..1ae81b59 100644 --- a/src/scoreboard/dependence_cell.py +++ b/src/scoreboard/dependence_cell.py @@ -89,14 +89,14 @@ class DependenceCell(Elaboratable): m.d.comb += src2_l.r.eq(self.go_rd_i) # FU "Forward Progress" (read out horizontally) - m.d.comb += self.dest_fwd_o.eq(dest_l.q & self.go_wr_i) - m.d.comb += self.src1_fwd_o.eq(src1_l.q & self.go_rd_i) - m.d.comb += self.src2_fwd_o.eq(src2_l.q & self.go_rd_i) + m.d.comb += self.dest_fwd_o.eq(dest_l.q & self.dest_i) + m.d.comb += self.src1_fwd_o.eq(src1_l.q & self.src1_i) + m.d.comb += self.src2_fwd_o.eq(src2_l.q & self.src2_i) # Register File Select (read out vertically) - m.d.sync += self.dest_rsel_o.eq(dest_l.q & self.dest_i) - m.d.sync += self.src1_rsel_o.eq(src1_l.q & self.src1_i) - m.d.sync += self.src2_rsel_o.eq(src2_l.q & self.src2_i) + m.d.sync += self.dest_rsel_o.eq(dest_l.q & ~self.go_wr_i) + m.d.sync += self.src1_rsel_o.eq(src1_l.q & ~self.go_rd_i) + m.d.sync += self.src2_rsel_o.eq(src2_l.q & ~self.go_rd_i) return m