From d7819df6dd02ef1593a57cedee805ba37dc9d97f Mon Sep 17 00:00:00 2001 From: Daniel Benusovich Date: Tue, 19 Mar 2019 22:05:50 -0700 Subject: [PATCH] Add PteEntry comments --- TLB/src/PteEntry.py | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/TLB/src/PteEntry.py b/TLB/src/PteEntry.py index 249251e8..c0705457 100644 --- a/TLB/src/PteEntry.py +++ b/TLB/src/PteEntry.py @@ -2,7 +2,37 @@ from nmigen import Module, Signal from nmigen.cli import main class PteEntry(): + """ The purpose of this Module is to centralize the parsing of Page + Table Entries (PTE) into one module to prevent common mistakes + and duplication of code. The control bits are parsed out for + ease of use. + + This module parses according to the standard PTE given by the + Volume II: RISC-V Privileged Architectures V1.10 Pg 60. + The Address Space IDentifier (ASID) is appended to the MSB of the input + and is parsed out as such. + + An valid input Signal would be: + ASID PTE + Bits:[78-64][63-0] + + The output PTE value will include the control bits. + """ def __init__(self, asid_size, pte_size): + """ Arguments: + * asid_size: (bit count) The size of the asid to be processed + * pte_size: (bit count) The size of the pte to be processed + + Return: + * d The Dirty bit from the PTE portion of i + * a The Accessed bit from the PTE portion of i + * g The Global bit from the PTE portion of i + * u The User Mode bit from the PTE portion of i + * xwr The Execute/Write/Read bit from the PTE portion of i + * v The Valid bit from the PTE portion of i + * asid The asid portion of i + * pte The pte portion of i + """ # Internal self.asid_start = pte_size self.asid_end = pte_size + asid_size -- 2.30.2