add dummy (fake) PLL to experiments10_verilog for testing
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Jun 2021 10:15:23 +0000 (10:15 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Jun 2021 10:15:34 +0000 (10:15 +0000)
commit18d4a3ff3df735d80aa87c0875157da4d15e1521
treef52b405683c282c7d691cb13a683f5040980d0fa
parent3f73dc23b438084fd3a0a34e25def7c5ddda3e49
add dummy (fake) PLL to experiments10_verilog for testing
experiments10_verilog/coriolis2/settings.py
experiments10_verilog/dummypll.py [new file with mode: 0644]
experiments10_verilog/non_generated/pll.v [new file with mode: 0644]
experiments10_verilog/pll.py [new file with mode: 0644]