sort out clock names in experiments10_verilog
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Jun 2021 11:30:42 +0000 (11:30 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Jun 2021 11:30:42 +0000 (11:30 +0000)
commit6e288c0869759266eef57a8aa7ddb62d3a1d2692
treecdcd05135cf50dd66a2c119e0b93635e229cbda5
parent913ad2a5a9145b15284fb7899d3aad90dd7a005a
sort out clock names in experiments10_verilog
experiments10_verilog/add.py
experiments10_verilog/coriolis2/settings.py
experiments10_verilog/doDesign.py