Merge pull request #3310 from robinsonb5-PRs/master
[yosys.git] / backends /
2022-05-09 Jannis HarderMerge pull request #3297 from jix/sva_nested_clk_else
2022-05-09 Miodrag MilanovićMerge pull request #3299 from YosysHQ/mmicko/sim_memory
2022-05-04 Claire Xenia WolfAdd propagated clock signals into btor info file
2022-04-25 Jannis HarderMerge pull request #3287 from jix/smt2-conditional...
2022-04-20 Jannis Hardersmt2: Make write port array stores conditional on nonze...
2022-04-08 Miodrag MilanovićMerge pull request #3273 from modwizcode/fix-build
2022-04-08 Aki Van Nesspass jny: flipped the defaults for the inclusion of...
2022-04-08 Aki Van Nesspass jny: ensured the cell collection is cleared betwee...
2022-04-08 Aki Van Nesspass jny: fixed missing quotes around the type value...
2022-04-08 Aki Van Nesspass jny: fixed the backslash escape for strings
2022-04-08 Aki Van Nesspass jny: removed the invalid json escapes
2022-04-08 Aki Van Nesspass jny: added some todo comments about things that...
2022-04-08 Aki Van Nesspass jny: changed the constructor initializers to use...
2022-04-08 Aki Van Nesspass jny: fixed the string escape method to be less...
2022-04-08 Aki Van Nesspass jny: fixed the signed output for param value output
2022-04-08 Aki Van Nesspass jny: added connection output
2022-04-08 Aki Van Nesspass jny: added filter options for including connection...
2022-04-08 Aki Van Nesspass jny: large chunk of refactoring to make the JSON...
2022-04-08 Aki Van Nessmetadata -> jny: migrated to the proper name for the...
2022-04-08 Aki Van Nesspass metadata: added the machinery to write param and...
2022-04-08 Aki Van Nesspass metadata: removed superfluous `stringf` calls
2022-04-08 Aki Van Nesspass metadata: some more rough work on dumping the...
2022-04-08 Aki Van Nesspass metadata: fixed the MetadataWriter object initiali...
2022-04-08 Aki Van Nesspass metadata: added the output of parameters,
2022-04-08 Aki Van Nesspass metadata: fixed some of the output formatting
2022-04-08 Aki Van Nesspass metadata: initial commit of the metadata pass...
2022-03-30 Miodrag MilanovićMerge pull request #3250 from YosysHQ/micko/verific_con...
2022-03-29 Miodrag MilanovićMerge pull request #3258 from jix/fix-no-assertions
2022-03-29 Jannis Hardersmtbmc: fix bmc with no assertions
2022-03-28 Jannis HarderMerge pull request #3253 from jix/smtbmc-nodeepcopy
2022-03-28 Jannis HarderMerge pull request #3247 from jix/smtbmc-keepgoing
2022-03-28 LoftyMerge pull request #3194 from Ravenslofty/abc9-flow3mfs
2022-03-28 LoftyMerge pull request #3246 from YosysHQ/gatecat/timing...
2022-03-28 Jannis Hardersmtbmc: Avoid unnecessary deep copies during unrolling
2022-03-25 Miodrag MilanovićMerge pull request #3249 from YosysHQ/micko/no_startoffset
2022-03-25 Miodrag MilanovicAdd -no-startoffset option to write_aiger
2022-03-24 Miodrag MilanovićMerge pull request #3243 from nakengelhardt/fix_aiw_comment
2022-03-24 Jannis Harderyosys-smtbmc: Option to keep going after failed asserti...
2022-03-24 Jannis Harderyosys-smtbmc: Fix typo in help text, remove trailing...
2022-03-24 N. Engelhardtignore # comment lines
2022-03-14 Claire XenMerge pull request #3213 from antonblanchard/abc-typo
2022-03-11 Miodrag MilanovićMerge pull request #3222 from zachjs/prune-linux-ci
2022-03-11 Miodrag MilanovićMerge pull request #3228 from YosysHQ/micko/disable_tests
2022-03-11 Miodrag MilanovićMerge pull request #3226 from YosysHQ/micko/btor2witness
2022-03-11 Claire Xenia WolfFix handling of some formal cells in btor back-end
2022-03-11 Miodrag Milanovichandle state names of $anyconst and $anyseq
2022-03-07 Miodrag MilanovićMerge pull request #3210 from rqou/json-signed
2022-03-04 Miodrag MilanovićMerge pull request #3186 from nakengelhardt/smtbmc_sby_...
2022-03-04 Miodrag MilanovićMerge pull request #3206 from YosysHQ/micko/quote_remove
2022-03-04 Miodrag MilanovićMerge pull request #3207 from nakengelhardt/json_escape...
2022-02-22 N. Engelhardtprint cell name for properties in yosys-smtbmc
2022-02-22 Claire XenMerge pull request #3211 from YosysHQ/micko/witness
2022-02-22 Claire XenMerge pull request #3197 from YosysHQ/claire/smtbmcfix
2022-02-22 Rjson: Add help message for `signed` field
2022-02-18 N. Engelhardtfix handling of escaped chars in json backend and frontend
2022-02-11 Claire Xenia WolfAdd a bit of flexibilty re trace length when processing...
2022-02-11 Miodrag MilanovićMerge pull request #3164 from zachjs/fix-ast-warn
2022-02-11 Claire XenMerge branch 'master' into clk2ff-better-names
2022-02-11 Claire XenMerge pull request #2019 from boqwxp/glift
2022-02-07 Miodrag MilanovićMerge pull request #3185 from YosysHQ/micko/co_sim
2022-01-31 Miodrag MilanovićMerge pull request #3176 from higuoxing/fix-ref-manual
2022-01-31 Marcelina Kościelnickaverilog backend: Emit a `wire` for ports as well.
2022-01-28 Marcelina KościelnickaAdd $bmux and $demux cells.
2022-01-19 Miodrag MilanovićMerge pull request #3120 from Icenowy/anlogic-bram
2021-12-25 CatherineMerge pull request #3127 from whitequark/cxxrtl-no...
2021-12-25 Catherinecxxrtl: don't reset elided wires with \init attribute.
2021-12-16 CatherineMerge pull request #3115 from whitequark/issue-3112
2021-12-15 Catherinecxxrtl: demote wires not inlinable only in debug_eval...
2021-12-12 Marcelina KościelnickaAdd clean_zerowidth pass, use it for Verilog output.
2021-12-12 CatherineMerge pull request #3105 from whitequark/cxxrtl-reset...
2021-12-12 Marcelina Kościelnickartlil: Dump empty connections when whole module is...
2021-12-11 Catherinecxxrtl: preserve interior memory pointers across reset.
2021-12-11 CatherineMerge pull request #3103 from whitequark/write_verilog...
2021-12-11 whitequarkcxxrtl: use unique_ptr<value<>[]> to store memory contents.
2021-12-11 whitequarkwrite_verilog: dump zero width sigspecs correctly.
2021-11-25 Loftysta: very crude static timing analysis pass
2021-11-17 Miodrag MilanovićMerge pull request #3080 from YosysHQ/micko/init_wire
2021-11-17 Miodrag MilanovicGive initial wire unique ID, fixes #2914
2021-10-11 Claire XenMerge pull request #3039 from YosysHQ/claire/verific_aldff
2021-10-11 Claire XenMerge pull request #3040 from YosysHQ/micko/split_modul...
2021-10-09 Miodrag MilanovicSplit module ports, 20 per line
2021-10-02 Marcelina KościelnickaHook up $aldff support in various passes.
2021-10-02 Marcelina Kościelnickakernel/ff: Refactor FfData to enable FFs with async...
2021-09-28 Miodrag MilanovićMerge pull request #3017 from YosysHQ/claire/short_rtli...
2021-09-27 Claire Xenia WolfAdd optimization to rtlil back-end for all-x parameter...
2021-09-18 Miodrag MilanovićMerge pull request #3010 from the6p4c/master
2021-09-17 the6p4cFix protobuf backend build dependencies
2021-09-10 Marcelina Kościelnickayosys-smtbmc: Fix reused loop variable.
2021-08-10 Marcelina Kościelnickakernel/mem: Introduce transparency masks.
2021-08-01 Marcelina Kościelnickabackend/verilog: Add alternate mode for transparent...
2021-07-28 Marcelina Kościelnickabackends/verilog: Support meminit with mask.
2021-07-20 whitequarkMerge pull request #2885 from whitequark/cxxrtl-fix...
2021-07-20 whitequarkMerge pull request #2884 from whitequark/cxxrtl-fix...
2021-07-20 whitequarkcxxrtl: treat wires with multiple defs as not inlinable.
2021-07-20 whitequarkcxxrtl: treat assignable internal wires used only for...
2021-07-20 whitequarkMerge pull request #2881 from whitequark/cxxrtl-sideway...
2021-07-19 whitequarkcxxrtl: escape colon in variable names in VCD writer.
2021-07-18 whitequarkMerge pull request #2880 from whitequark/cxxrtl-fix...
2021-07-18 whitequarkcxxrtl: add debug_item::{get,set}.
2021-07-17 whitequarkMerge pull request #2879 from whitequark/cxxrtl-fix...
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