Merge pull request #3310 from robinsonb5-PRs/master
[yosys.git] / passes /
2022-05-17 Miodrag MilanovićMerge pull request #3310 from robinsonb5-PRs/master master
2022-05-17 Marcelina Kościelnickaopt_ffinv: Use ModIndex instead of ModWalker.
2022-05-16 Jannis HarderMerge pull request #3314 from jix/sva_value_change_logi...
2022-05-13 Marcelina KościelnickaAdd opt_ffinv pass.
2022-05-12 Marcelina KościelnickaAdd proc_rom pass.
2022-05-09 Jannis HarderMerge pull request #3297 from jix/sva_nested_clk_else
2022-05-09 Miodrag MilanovićMerge pull request #3299 from YosysHQ/mmicko/sim_memory
2022-05-07 Marcelina Kościelnickaopt_mem: Remove constant-value bit lanes.
2022-05-06 Miodrag MilanovićMerge pull request #3300 from imhcyx/master
2022-05-05 imhcyxmemory_share: fix wrong argidx in extra_args
2022-05-04 Marcelina Kościelnickaabc: Use dict/pool instead of std::map/std::set
2022-05-04 Miodrag Milanovicfix crash when no fst input
2022-05-04 Miodrag MilanovicStart restoring memory state from VCD/FST
2022-05-02 Miodrag MilanovicAIM file could have gaps in or between inputs and inits
2022-04-25 Jannis HarderMerge pull request #3287 from jix/smt2-conditional...
2022-04-25 Jannis HarderMerge pull request #3257 from jix/tribuf-formal
2022-04-25 Miodrag MilanovićMerge pull request #3290 from mpasternacki/bugfix/freeb...
2022-04-25 Miodrag MilanovićMerge pull request #3289 from YosysHQ/micko/sim_improve
2022-04-22 Miodrag MilanovicMatch $anyseq input if connected to public wire
2022-04-22 Miodrag MilanovicTreat $anyseq as input from FST
2022-04-22 Miodrag MilanovicLast sample from input does not represent change
2022-04-22 Miodrag Milanoviclatches are always set to zero
2022-04-22 Miodrag MilanovicIf not multiclock, output only on clock edges
2022-04-22 Miodrag MilanovicSet init state for all wires from FST and set past
2022-04-22 Miodrag MilanovicFix multiclock for btor2 witness
2022-04-18 Miodrag MilanovićMerge pull request #3280 from YosysHQ/micko/fix_readaiw
2022-04-18 Miodrag MilanovićMerge pull request #3282 from nakengelhardt/verific_loo...
2022-04-15 Marcelina Kościelnickamemory_share: Fix up mismatched address widths.
2022-04-15 Marcelina Kościelnickaopt_dff: Fix behavior on $ff with D == Q.
2022-04-15 Miodrag MilanovicFix reading aiw from other solvers
2022-04-12 Jannis Hardertribuf: `-formal` option: convert all to logic and...
2022-04-08 Miodrag MilanovićMerge pull request #3275 from YosysHQ/micko/clk2fflogic_fix
2022-04-08 Miodrag MilanovicUse wrap_async_control_gate if ff is fine
2022-04-08 Miodrag MilanovićMerge pull request #3273 from modwizcode/fix-build
2022-04-08 Iris JohnsonMakefile: properly conditionalize features requiring...
2022-04-07 CatherineMerge pull request #3269 from YosysHQ/micko/fix_autotop
2022-04-07 Marcelina Kościelnickaabc: Add support for FFs with reset in -dff
2022-04-05 Miodrag MilanovicReorder steps in -auto-top to fix synth command, fixes...
2022-04-04 Marcelina Kościelnickashow: Fix width labels.
2022-04-04 Miodrag MilanovićMerge pull request #3265 from YosysHQ/micko/sim_improve...
2022-04-02 Miodrag Milanovicpast_ad initial value setting
2022-04-02 Miodrag MilanovicsetInitState can be only one altering values
2022-04-02 Miodrag MilanovicSet past_d value for init state
2022-04-02 Jannis HarderMerge pull request #3264 from jix/invalid_ff_dcinit_merge
2022-04-01 Jannis Harderopt_merge: Add `-keepdc` option required for formal...
2022-04-01 Miodrag MilanovićMerge pull request #3263 from YosysHQ/micko/clk2ff_init
2022-04-01 Miodrag MilanovicSet init values for wrapped async control signals
2022-03-31 Miodrag MilanovićMerge pull request #3256 from YosysHQ/micko/aiw_multiclock
2022-03-31 Miodrag Milanovic Support memories in aiw and multiclock
2022-03-30 Miodrag MilanovićMerge pull request #3250 from YosysHQ/micko/verific_con...
2022-03-28 Jannis HarderMerge pull request #3253 from jix/smtbmc-nodeepcopy
2022-03-28 Jannis HarderMerge pull request #3247 from jix/smtbmc-keepgoing
2022-03-28 LoftyMerge pull request #3194 from Ravenslofty/abc9-flow3mfs
2022-03-28 LoftyMerge pull request #3246 from YosysHQ/gatecat/timing...
2022-03-24 gatecatabc9_ops: Also derive blackboxes with timing info
2022-03-22 Miodrag MilanovicProper SigBit forming in sim
2022-03-22 Miodrag MilanovicProper SigBit forming in sim
2022-03-18 Miodrag MilanovicMore verbose warnings
2022-03-17 Miodrag MilanovićMerge pull request #3236 from YosysHQ/micko/tb_initial
2022-03-16 Miodrag MilanovicRecognize registers and set initial state for them...
2022-03-16 Miodrag MilanovicUpdate sim help message.
2022-03-14 Miodrag MilanovićMerge pull request #3232 from YosysHQ/micko/fst2tb
2022-03-14 Miodrag MilanovicAdded fst2tb pass for generating testbench
2022-03-14 Claire XenMerge pull request #3213 from antonblanchard/abc-typo
2022-03-11 Miodrag MilanovićMerge pull request #3229 from YosysHQ/micko/sim_date
2022-03-11 Miodrag MilanovićMerge pull request #3222 from zachjs/prune-linux-ci
2022-03-11 Miodrag MilanovićMerge pull request #3228 from YosysHQ/micko/disable_tests
2022-03-11 Claire Xenia WolfAdd "sim -q" option
2022-03-11 Miodrag MilanovicAdd date parameter to enable full date/time and version...
2022-03-11 Claire Xenia WolfSmall fix in "sim" help message
2022-03-11 Miodrag MilanovićMerge pull request #3226 from YosysHQ/micko/btor2witness
2022-03-11 Miodrag MilanovicFstData already do conversion to VCD
2022-03-11 Miodrag MilanovicSupport cell name in btor witness file
2022-03-11 Miodrag MilanovicProper write of memory data
2022-03-09 Miodrag MilanovicStart work on memory init
2022-03-09 Miodrag MilanovicFixes and error check
2022-03-07 Miodrag Milanoviccleanup
2022-03-07 Miodrag MilanovicError checks for aiger witness
2022-03-07 Miodrag Milanovicbtor2 witness co-simulation
2022-03-07 Miodrag MilanovićMerge pull request #3210 from rqou/json-signed
2022-03-04 Miodrag MilanovićMerge pull request #3186 from nakengelhardt/smtbmc_sby_...
2022-03-04 Miodrag MilanovićMerge pull request #3206 from YosysHQ/micko/quote_remove
2022-03-04 Miodrag MilanovićMerge pull request #3207 from nakengelhardt/json_escape...
2022-03-04 Miodrag MilanovićMerge pull request #3219 from YosysHQ/micko/quick_vcd
2022-03-04 Miodrag MilanovićMerge pull request #3220 from YosysHQ/claire/simstuff
2022-03-02 Miodrag MilanovicAdd option to ignore X only signals in output
2022-03-02 Miodrag MilanovicWrite simulation files after simulation is performed
2022-03-02 Claire XenMerge pull request #3224 from YosysHQ/micko/refactor
2022-03-02 Miodrag MilanovicCleanup
2022-02-28 Miodrag MilanovicRefactor sim output writers
2022-02-28 Miodrag MilanovicQuick fix
2022-02-28 Claire Xenia WolfAdd writing of aiw files to "sim" command
2022-02-28 Claire Xenia WolfHotfix in AIGER witness reader state machine
2022-02-28 Miodrag MilanovicVCD reader support by using external tool
2022-02-28 Miodrag MilanovićMerge pull request #3216 from YosysHQ/claire/simstuff
2022-02-27 Miodrag MilanovicSupport extended aiw format
2022-02-25 Miodrag MilanovicFix for last clock edge data
2022-02-25 Claire Xenia WolfExperimental sim changes
2022-02-23 Anton Blanchardabc: Fix {I} and {P} substitution
2022-02-22 Claire XenMerge pull request #3211 from YosysHQ/micko/witness
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