yosys.git
2022-03-04 Miodrag MilanovicRelease version 0.15 yosys-0.15
2022-03-04 Miodrag MilanovicUpdate ABC
2022-03-04 Miodrag MilanovicUpdate documentation
2022-03-04 Miodrag MilanovićMerge pull request #3219 from YosysHQ/micko/quick_vcd
2022-03-04 Miodrag MilanovićMerge pull request #3220 from YosysHQ/claire/simstuff
2022-03-03 github-actions... Bump version
2022-03-02 Miodrag MilanovicAdd option to ignore X only signals in output
2022-03-02 Miodrag MilanovicWrite simulation files after simulation is performed
2022-03-02 Miodrag MilanovicUpdate CHANGELOG
2022-03-02 Claire XenMerge pull request #3224 from YosysHQ/micko/refactor
2022-03-02 Miodrag MilanovicCleanup
2022-03-01 github-actions... Bump version
2022-02-28 Miodrag MilanovicRefactor sim output writers
2022-02-28 Miodrag MilanovicQuick fix
2022-02-28 Claire Xenia... Add writing of aiw files to "sim" command
2022-02-28 Claire Xenia... Hotfix in AIGER witness reader state machine
2022-02-28 Miodrag MilanovicVCD reader support by using external tool
2022-02-28 Miodrag MilanovićMerge pull request #3216 from YosysHQ/claire/simstuff
2022-02-27 Miodrag MilanovicSupport extended aiw format
2022-02-25 Miodrag MilanovicFix for last clock edge data
2022-02-25 Claire Xenia... Experimental sim changes
2022-02-25 github-actions... Bump version
2022-02-24 YRabbitgowin: Remove unnecessary attributes
2022-02-24 YRabbitgowin: Add support for true differential output
2022-02-22 Claire XenMerge pull request #3211 from YosysHQ/micko/witness
2022-02-22 Claire XenMerge pull request #3197 from YosysHQ/claire/smtbmcfix
2022-02-22 github-actions... Bump version
2022-02-21 Miodrag MilanovićMerge pull request #3203 from YosysHQ/micko/sim_ff
2022-02-21 Marcelina Kościelnickaecp5: Do not use specify in generate in cells_sim.v.
2022-02-21 Miodrag MilanovicFix handling of ce_over_srst
2022-02-18 Claire Xenia... Fix cycle 0 in aiger witness co-simulation
2022-02-18 Miodrag MilanovicChanged error message
2022-02-18 Miodrag MilanovicAdded AIGER witness file co simulation
2022-02-18 Miodrag Milanovicsimplify logic of handling flip-flops and latches
2022-02-17 Miodrag MilanovicReview cleanup
2022-02-16 Miodrag Milanovictest dlatchsr and adlatch
2022-02-16 Miodrag MilanovicAdded test cases
2022-02-16 Miodrag MilanovicAdd support for various ff/latch cells simulation
2022-02-16 github-actions... Bump version
2022-02-15 Miodrag MilanovićMerge pull request #3204 from YosysHQ/claire/update-abc
2022-02-15 Miodrag MilanovicBump ABC version
2022-02-15 github-actions... Bump version
2022-02-14 Zachary Snowverilog: support for time scale delay values
2022-02-14 Kamil RakoczyFix access to whole sub-structs (#3086)
2022-02-13 github-actions... Bump version
2022-02-12 Marcelina Kościelnickagowin: Add remaining block RAM blackboxes.
2022-02-12 github-actions... Bump version
2022-02-11 Zachary Snowverilog: fix dynamic dynamic range asgn elab
2022-02-11 Zachary Snowverilog: fix const func eval with upto variables
2022-02-11 Claire XenMerge pull request #2376 from nmoroze/clk2ff-better...
2022-02-11 Claire Xenia... Add a bit of flexibilty re trace length when processing...
2022-02-11 Miodrag MilanovićMerge pull request #3164 from zachjs/fix-ast-warn
2022-02-11 Claire XenMerge branch 'master' into clk2ff-better-names
2022-02-11 Claire XenMerge pull request #2019 from boqwxp/glift
2022-02-10 github-actions... Bump version
2022-02-09 Miodrag MilanovićMerge pull request #3193 from YosysHQ/micko/verific_f
2022-02-09 Miodrag MilanovicAdd ability to override verilog mode for verific -f...
2022-02-09 Marcelina Kościelnickagowin: Fix LUT RAM inference, add more models.
2022-02-09 Marcelina Kościelnickaecp5: Fix DPR16X4 sim model.
2022-02-08 github-actions... Bump version
2022-02-07 Miodrag MilanovicNext dev cycle
2022-02-07 Miodrag MilanovicRelease version 0.14 yosys-0.14
2022-02-07 Miodrag MilanovicUpdate CHANGELOG and manual
2022-02-07 Miodrag MilanovićMerge pull request #3185 from YosysHQ/micko/co_sim
2022-02-07 github-actions... Bump version
2022-02-06 Marcelina Kościelnickanexus: Fix arith_map CO signal.
2022-02-04 Miodrag MilanovicError detection for co-simulation
2022-02-04 Miodrag Milanovicbug fix and cleanups
2022-02-03 github-actions... Bump version
2022-02-02 Miodrag MilanovićMerge pull request #3183 from YosysHQ/micko/nto1mux
2022-02-02 Miodrag MilanovicUse bmux for NTO1MUX
2022-02-02 Miodrag MilanovicAdd test cases for co-simulation
2022-02-02 Miodrag MilanovićMerge pull request #3182 from yrabbit/wip-doc2
2022-02-02 YRabbitCorrect a typo in the manual
2022-02-02 Miodrag MilanovicFix Visual Studio build
2022-02-02 Miodrag Milanovicrespect hide_internal flag
2022-02-02 Miodrag Milanovicunify cycles counting and cleanup
2022-02-02 Miodrag Milanovicadded stimulus mode and param check
2022-02-02 Scott ThibaultUpdate comment
2022-02-02 Scott ThibaultFix unextend method for signed constants
2022-01-31 Miodrag Milanovicerror when no signal found
2022-01-31 Miodrag MilanovićMerge pull request #3176 from higuoxing/fix-ref-manual
2022-01-31 Miodrag MilanovicCleanup
2022-01-31 Miodrag MilanovicCompare bits when not all are defined
2022-01-31 Miodrag MilanovicCleanup
2022-01-31 Miodrag Milanovicmessage update
2022-01-31 Miodrag MilanovicDisplay simulation time data
2022-01-31 Miodrag MilanovicUse edges when explicit
2022-01-31 Miodrag MilanovicUpdating initial state and checks
2022-01-31 Miodrag MilanovicFix scope
2022-01-31 github-actions... Bump version
2022-01-31 Marcelina Kościelnickaverilog backend: Emit a `wire` for ports as well.
2022-01-30 Xing GUOFix the help message of synth_quicklogic.
2022-01-30 Marcelina Kościelnickaopt_reduce: Add $bmux and $demux optimization patterns.
2022-01-29 github-actions... Bump version
2022-01-28 Marcelina KościelnickaAdd $bmux and $demux cells.
2022-01-28 Miodrag Milanoviccheck if stop before start
2022-01-28 Miodrag Milanovicset initial state, only flip-flops
2022-01-28 Miodrag Milanovicignore not found private signals
2022-01-28 Miodrag Milanovicpreserve VCD mangled names
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