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  26 Subject: Re: [libre-riscv-dev] minimum viable ASIC
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  55 Luke Kenneth Casson Leighton schreef op vr 08-05-2020 om 10:50 [+0100]:
  56 >=20
  57 > * a PLL (this is quite a lot however it turns the ASIC from a 24mhz
  58 > design into a 300mhz design)
  59
  60 Why only 24MHz without PLL ? You should have problems getting external
  61 clock frequencies up to 100MHz without a problem inside a chip.
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