CHANGELOG

   1
   2 List of major changes and improvements between releases
   3 =======================================================
   4
   5 Yosys 0.12 .. Yosys 0.12-dev
   6 --------------------------
   7
   8 Yosys 0.11 .. Yosys 0.12
   9 --------------------------
  10
  11  * Various
  12     - Added iopadmap native support for negative-polarity output enable
  13     - ABC update
  14
  15  * SystemVerilog
  16     - Support parameters using struct as a wiretype
  17
  18  * New commands and options
  19     - Added "-genlib" option to "abc" pass
  20     - Added "sta" very crude static timing analysis pass
  21
  22  * Verific support
  23     - Fixed memory block size in import
  24
  25  * New back-ends
  26     - Added support for GateMate FPGA from Cologne Chip AG
  27
  28  * Intel ALM support
  29     - Added preliminary Arria V support
  30
  31
  32 Yosys 0.10 .. Yosys 0.11
  33 --------------------------
  34
  35  * Various
  36     - Added $aldff and $aldffe (flip-flops with async load) cells
  37
  38  * SystemVerilog
  39     - Fixed an issue which prevented writing directly to a memory word via a
  40       connection to an output port
  41     - Fixed an issue which prevented unbased unsized literals (e.g., `'1`) from
  42       filling the width of a cell input
  43     - Fixed an issue where connecting a slice covering the entirety of a signed
  44       signal to a cell input would cause a failed assertion
  45
  46  * Verific support
  47     - Importer support for {PRIM,WIDE_OPER}_DFF
  48     - Importer support for PRIM_BUFIF1
  49     - Option to use Verific without VHDL support
  50     - Importer support for {PRIM,WIDE_OPER}_DLATCH{,RS}
  51     - Added -cfg option for getting/setting Verific runtime flags
  52
  53 Yosys 0.9 .. Yosys 0.10
  54 --------------------------
  55
  56  * Various
  57     - Added automatic gzip decompression for frontends
  58     - Added $_NMUX_ cell type
  59     - Added automatic gzip compression (based on filename extension) for backends
  60     - Improve attribute and parameter encoding in JSON to avoid ambiguities between
  61       bit vectors and strings containing [01xz]*
  62     - Improvements in pmgen: subpattern and recursive matches
  63     - Support explicit FIRRTL properties
  64     - Improvements in pmgen: slices, choices, define, generate
  65     - Added "_TECHMAP_WIREINIT_*_" parameter and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
  66     - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
  67     - Added new frontend: rpc
  68     - Added --version and -version as aliases for -V
  69     - Improve yosys-smtbmc "solver not found" handling
  70     - Improved support of $readmem[hb] Memory Content File inclusion
  71     - Added CXXRTL backend
  72     - Use YosysHQ/abc instead of upstream berkeley-abc/abc
  73     - Added WASI platform support.
  74     - Added extmodule support to firrtl backend
  75     - Added $divfloor and $modfloor cells
  76     - Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells
  77     - Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass
  78     - Added firrtl backend support for generic parameters in blackbox components
  79     - Added $meminit_v2 cells (with support for write mask)
  80     - Added $mem_v2, $memrd_v2, $memwr_v2, with the following features:
  81       - write priority masks, per write/write port pair
  82       - transparency and undefined collision behavior masks, per read/write port pair
  83       - read port reset and initialization
  84       - wide ports (accessing a naturally aligned power-of-two number of memory cells)
  85
  86  * New commands and options
  87     - Added "write_xaiger" backend
  88     - Added "read_xaiger"
  89     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only)
  90     - Added "synth -abc9" (experimental)
  91     - Added "script -scriptwire"
  92     - Added "clkbufmap" pass
  93     - Added "extractinv" pass and "invertible_pin" attribute
  94     - Added "proc_clean -quiet"
  95     - Added "proc_prune" pass
  96     - Added "stat -tech cmos"
  97     - Added "opt_share" pass, run as part of "opt -full"
  98     - Added "-match-init" option to "dff2dffs" pass
  99     - Added "equiv_opt -multiclock"
 100     - Added "techmap_autopurge" support to techmap
 101     - Added "add -mod <modname[s]>"
 102     - Added "paramap" pass
 103     - Added "portlist" command
 104     - Added "check -mapped"
 105     - Added "check -allow-tbuf"
 106     - Added "autoname" pass
 107     - Added "write_verilog -extmem"
 108     - Added "opt_mem" pass
 109     - Added "scratchpad" pass
 110     - Added "fminit" pass
 111     - Added "opt_lut_ins" pass
 112     - Added "logger" pass
 113     - Added "show -nobg"
 114     - Added "exec" command
 115     - Added "design -delete"
 116     - Added "design -push-copy"
 117     - Added "qbfsat" command
 118     - Added "select -unset"
 119     - Added "dfflegalize" pass
 120     - Removed "opt_expr -clkinv" option, made it the default
 121     - Added "proc -nomux
 122     - Merged "dffsr2dff", "opt_rmdff", "dff2dffe", "dff2dffs", "peepopt.dffmux" passes into a new "opt_dff" pass
 123
 124  * SystemVerilog
 125     - Added checking of always block types (always_comb, always_latch and always_ff)
 126     - Added support for wildcard port connections (.*)
 127     - Added support for enum typedefs
 128     - Added support for structs and packed unions.
 129     - Allow constant function calls in for loops and generate if and case
 130     - Added support for static cast
 131     - Added support for logic typed parameters
 132     - Fixed generate scoping issues
 133     - Added support for real-valued parameters
 134     - Allow localparams in constant functions
 135     - Module name scope support
 136     - Support recursive functions using ternary expressions
 137     - Extended support for integer types
 138     - Support for parameters without default values
 139     - Allow globals in one file to depend on globals in another
 140     - Added support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
 141     - Added support for parsing the 'bind' construct
 142     - support declaration in procedural for initialization
 143     - support declaration in generate for initialization
 144     - Support wand and wor of data types
 145
 146  * Verific support
 147     - Added "verific -L"
 148     - Add Verific SVA support for "always" properties
 149     - Add Verific support for SVA nexttime properties
 150     - Improve handling of verific primitives in "verific -import -V" mode
 151     - Import attributes for wires
 152     - Support VHDL enums
 153     - Added support for command files
 154
 155  * New back-ends
 156     - Added initial EFINIX support
 157     - Added Intel ALM: alternative synthesis for Intel FPGAs
 158     - Added initial Nexus support
 159     - Added initial MachXO2 support
 160     - Added initial QuickLogic PolarPro 3 support
 161
 162  * ECP5 support
 163     - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 164     - Added "synth_ecp5 -abc9" (experimental)
 165     - Added "synth_ecp5 -nowidelut"
 166     - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
 167
 168  * iCE40 support
 169     - Added "synth_ice40 -abc9" (experimental)
 170     - Added "synth_ice40 -device"
 171     - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 172     - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
 173     - Removed "ice40_unlut"
 174     - Added "ice40_dsp" for Lattice iCE40 DSP packing
 175     - "synth_ice40 -dsp" to infer DSP blocks
 176
 177  * Xilinx support
 178     - Added "synth_xilinx -abc9" (experimental)
 179     - Added "synth_xilinx -nocarry"
 180     - Added "synth_xilinx -nowidelut"
 181     - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
 182     - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
 183     - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
 184     - Added "synth_xilinx -ise" (experimental)
 185     - Added "synth_xilinx -iopad"
 186     - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
 187     - Added "xilinx_srl" for Xilinx shift register extraction
 188     - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
 189     - Added "xilinx_dsp" for Xilinx DSP packing
 190     - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
 191     - Added latch support to synth_xilinx
 192     - Added support for flip-flops with synchronous reset to synth_xilinx
 193     - Added support for flip-flops with reset and enable to synth_xilinx
 194     - Added "xilinx_dffopt" pass
 195     - Added "synth_xilinx -dff"
 196
 197  * Intel support
 198     - Renamed labels in synth_intel (e.g. bram -> map_bram)
 199     - synth_intel: cyclone10 -> cyclone10lp, a10gx -> arria10gx
 200     - Added "intel_alm -abc9" (experimental)
 201
 202  * CoolRunner2 support
 203     - Separate and improve buffer cell insertion pass
 204     - Use extract_counter to optimize counters
 205
 206 Yosys 0.8 .. Yosys 0.9
 207 ----------------------
 208
 209  * Various
 210     - Many bugfixes and small improvements
 211     - Added support for SystemVerilog interfaces and modports
 212     - Added "write_edif -attrprop"
 213     - Added "opt_lut" pass
 214     - Added "gate2lut.v" techmap rule
 215     - Added "rename -src"
 216     - Added "equiv_opt" pass
 217     - Added "flowmap" LUT mapping pass
 218     - Added "rename -wire" to rename cells based on the wires they drive
 219     - Added "bugpoint" for creating minimised testcases
 220     - Added "write_edif -gndvccy"
 221     - "write_verilog" to escape Verilog keywords
 222     - Fixed sign handling of real constants
 223     - "write_verilog" to write initial statement for initial flop state
 224     - Added pmgen pattern matcher generator
 225     - Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
 226     - Added "setundef -params" to replace undefined cell parameters
 227     - Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
 228     - Fixed handling of defparam when default_nettype is none
 229     - Fixed "wreduce" flipflop handling
 230     - Fixed FIRRTL to Verilog process instance subfield assignment
 231     - Added "write_verilog -siminit"
 232     - Several fixes and improvements for mem2reg memories
 233     - Fixed handling of task output ports in clocked always blocks
 234     - Improved handling of and-with-1 and or-with-0 in "opt_expr"
 235     - Added "read_aiger" frontend
 236     - Added "mutate" pass
 237     - Added "hdlname" attribute
 238     - Added "rename -output"
 239     - Added "read_ilang -lib"
 240     - Improved "proc" full_case detection and handling
 241     - Added "whitebox" and "lib_whitebox" attributes
 242     - Added "read_verilog -nowb", "flatten -wb" and "wbflip"
 243     - Added Python bindings and support for Python plug-ins
 244     - Added "pmux2shiftx"
 245     - Added log_debug framework for reduced default verbosity
 246     - Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
 247     - Added "peepopt" peephole optimisation pass using pmgen
 248     - Added approximate support for SystemVerilog "var" keyword
 249     - Added parsing of "specify" blocks into $specrule and $specify[23]
 250     - Added support for attributes on parameters and localparams
 251     - Added support for parsing attributes on port connections
 252     - Added "wreduce -keepdc"
 253     - Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
 254     - Added Verilog wand/wor wire type support
 255     - Added support for elaboration system tasks
 256     - Added "muxcover -mux{4,8,16}=<cost>"
 257     - Added "muxcover -dmux=<cost>"
 258     - Added "muxcover -nopartial"
 259     - Added "muxpack" pass
 260     - Added "pmux2shiftx -norange"
 261     - Added support for "~" in filename parsing
 262     - Added "read_verilog -pwires" feature to turn parameters into wires
 263     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
 264     - Fixed genvar to be a signed type
 265     - Added support for attributes on case rules
 266     - Added "upto" and "offset" to JSON frontend and backend
 267     - Several liberty file parser improvements
 268     - Fixed handling of more complex BRAM patterns
 269     - Add "write_aiger -I -O -B"
 270
 271  * Formal Verification
 272     - Added $changed support to read_verilog
 273     - Added "read_verilog -noassert -noassume -assert-assumes"
 274     - Added btor ops for $mul, $div, $mod and $concat
 275     - Added yosys-smtbmc support for btor witnesses
 276     - Added "supercover" pass
 277     - Fixed $global_clock handling vs autowire
 278     - Added $dffsr support to "async2sync"
 279     - Added "fmcombine" pass
 280     - Added memory init support in "write_btor"
 281     - Added "cutpoint" pass
 282     - Changed "ne" to "neq" in btor2 output
 283     - Added support for SVA "final" keyword
 284     - Added "fmcombine -initeq -anyeq"
 285     - Added timescale and generated-by header to yosys-smtbmc vcd output
 286     - Improved BTOR2 handling of undriven wires
 287
 288  * Verific support
 289     - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
 290     - Improved support for asymmetric memories
 291     - Added "verific -chparam"
 292     - Fixed "verific -extnets" for more complex situations
 293     - Added "read -verific" and "read -noverific"
 294     - Added "hierarchy -chparam"
 295
 296  * New back-ends
 297     - Added initial Anlogic support
 298     - Added initial SmartFusion2 and IGLOO2 support
 299
 300  * ECP5 support
 301     - Added "synth_ecp5 -nowidelut"
 302     - Added BRAM inference support to "synth_ecp5"
 303     - Added support for transforming Diamond IO and flipflop primitives
 304
 305  * iCE40 support
 306     - Added "ice40_unlut" pass
 307     - Added "synth_ice40 -relut"
 308     - Added "synth_ice40 -noabc"
 309     - Added "synth_ice40 -dffe_min_ce_use"
 310     - Added DSP inference support using pmgen
 311     - Added support for initialising BRAM primitives from a file
 312     - Added iCE40 Ultra RGB LED driver cells
 313
 314  * Xilinx support
 315     - Use "write_edif -pvector bra" for Xilinx EDIF files
 316     - Fixes for VPR place and route support with "synth_xilinx"
 317     - Added more cell simulation models
 318     - Added "synth_xilinx -family"
 319     - Added "stat -tech xilinx" to estimate logic cell usage
 320     - Added "synth_xilinx -nocarry"
 321     - Added "synth_xilinx -nowidelut"
 322     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 323     - Added support for mapping RAM32X1D
 324
 325 Yosys 0.7 .. Yosys 0.8
 326 ----------------------
 327
 328  * Various
 329     - Many bugfixes and small improvements
 330     - Strip debug symbols from installed binary
 331     - Replace -ignore_redef with -[no]overwrite in front-ends
 332     - Added write_verilog hex dump support, add -nohex option
 333     - Added "write_verilog -decimal"
 334     - Added "scc -set_attr"
 335     - Added "verilog_defines" command
 336     - Remember defines from one read_verilog to next
 337     - Added support for hierarchical defparam
 338     - Added FIRRTL back-end
 339     - Improved ABC default scripts
 340     - Added "design -reset-vlog"
 341     - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
 342     - Added Verilog $rtoi and $itor support
 343     - Added "check -initdrv"
 344     - Added "read_blif -wideports"
 345     - Added support for SystemVerilog "++" and "--" operators
 346     - Added support for SystemVerilog unique, unique0, and priority case
 347     - Added "write_edif" options for edif "flavors"
 348     - Added support for resetall compiler directive
 349     - Added simple C beck-end (bitwise combinatorical only atm)
 350     - Added $_ANDNOT_ and $_ORNOT_ cell types
 351     - Added cell library aliases to "abc -g"
 352     - Added "setundef -anyseq"
 353     - Added "chtype" command
 354     - Added "design -import"
 355     - Added "write_table" command
 356     - Added "read_json" command
 357     - Added "sim" command
 358     - Added "extract_fa" and "extract_reduce" commands
 359     - Added "extract_counter" command
 360     - Added "opt_demorgan" command
 361     - Added support for $size and $bits SystemVerilog functions
 362     - Added "blackbox" command
 363     - Added "ltp" command
 364     - Added support for editline as replacement for readline
 365     - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
 366     - Added "yosys -E" for creating Makefile dependencies files
 367     - Added "synth -noshare"
 368     - Added "memory_nordff"
 369     - Added "setundef -undef -expose -anyconst"
 370     - Added "expose -input"
 371     - Added specify/specparam parser support (simply ignore them)
 372     - Added "write_blif -inames -iattr"
 373     - Added "hierarchy -simcheck"
 374     - Added an option to statically link abc into yosys
 375     - Added protobuf back-end
 376     - Added BLIF parsing support for .conn and .cname
 377     - Added read_verilog error checking for reg/wire/logic misuse
 378     - Added "make coverage" and ENABLE_GCOV build option
 379
 380  * Changes in Yosys APIs
 381     - Added ConstEval defaultval feature
 382     - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
 383     - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
 384     - Added log_file_warning() and log_file_error() functions
 385
 386  * Formal Verification
 387     - Added "write_aiger"
 388     - Added "yosys-smtbmc --aig"
 389     - Added "always <positive_int>" to .smtc format
 390     - Added $cover cell type and support for cover properties
 391     - Added $fair/$live cell type and support for liveness properties
 392     - Added smtbmc support for memory vcd dumping
 393     - Added "chformal" command
 394     - Added "write_smt2 -stbv" and "write_smt2 -stdt"
 395     - Fix equiv_simple, old behavior now available with "equiv_simple -short"
 396     - Change to Yices2 as default SMT solver (it is GPL now)
 397     - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
 398     - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
 399     - Added a brand new "write_btor" command for BTOR2
 400     - Added clk2fflogic memory support and other improvements
 401     - Added "async memory write" support to write_smt2
 402     - Simulate clock toggling in yosys-smtbmc VCD output
 403     - Added $allseq/$allconst cells for EA-solving
 404     - Make -nordff the default in "prep"
 405     - Added (* gclk *) attribute
 406     - Added "async2sync" pass for single-clock designs with async resets
 407
 408  * Verific support
 409     - Many improvements in Verific front-end
 410     - Added proper handling of concurent SVA properties
 411     - Map "const" and "rand const" to $anyseq/$anyconst
 412     - Added "verific -import -flatten" and "verific -import -extnets"
 413     - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
 414     - Remove PSL support (because PSL has been removed in upstream Verific)
 415     - Improve integration with "hierarchy" command design elaboration
 416     - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
 417     - Added simpilied "read" command that automatically uses verific if available
 418     - Added "verific -set-<severity> <msg_id>.."
 419     - Added "verific -work <libname>"
 420
 421  * New back-ends
 422     - Added initial Coolrunner-II support
 423     - Added initial eASIC support
 424     - Added initial ECP5 support
 425
 426  * GreenPAK Support
 427     - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
 428
 429  * iCE40 Support
 430     - Add "synth_ice40 -vpr"
 431     - Add "synth_ice40 -nodffe"
 432     - Add "synth_ice40 -json"
 433     - Add Support for UltraPlus cells
 434
 435  * MAX10 and Cyclone IV Support
 436     - Added initial version of metacommand "synth_intel".
 437     - Improved write_verilog command to produce VQM netlist for Quartus Prime.
 438     - Added support for MAX10 FPGA family synthesis.
 439     - Added support for Cyclone IV family synthesis.
 440     - Added example of implementation for DE2i-150 board.
 441     - Added example of implementation for MAX10 development kit.
 442     - Added LFSR example from Asic World.
 443     - Added "dffinit -highlow" for mapping to Intel primitives
 444
 445
 446 Yosys 0.6 .. Yosys 0.7
 447 ----------------------
 448
 449  * Various
 450     - Added "yosys -D" feature
 451     - Added support for installed plugins in $(DATDIR)/plugins/
 452     - Renamed opt_const to opt_expr
 453     - Renamed opt_share to opt_merge
 454     - Added "prep -flatten" and "synth -flatten"
 455     - Added "prep -auto-top" and "synth -auto-top"
 456     - Using "mfs" and "lutpack" in ABC lut mapping
 457     - Support for abstract modules in chparam
 458     - Cleanup abstract modules at end of "hierarchy -top"
 459     - Added tristate buffer support to iopadmap
 460     - Added opt_expr support for div/mod by power-of-two
 461     - Added "select -assert-min <N> -assert-max <N>"
 462     - Added "attrmvcp" pass
 463     - Added "attrmap" command
 464     - Added "tee +INT -INT"
 465     - Added "zinit" pass
 466     - Added "setparam -type"
 467     - Added "shregmap" pass
 468     - Added "setundef -init"
 469     - Added "nlutmap -assert"
 470     - Added $sop cell type and "abc -sop -I <num> -P <num>"
 471     - Added "dc2" to default ABC scripts
 472     - Added "deminout"
 473     - Added "insbuf" command
 474     - Added "prep -nomem"
 475     - Added "opt_rmdff -keepdc"
 476     - Added "prep -nokeepdc"
 477     - Added initial version of "synth_gowin"
 478     - Added "fsm_expand -full"
 479     - Added support for fsm_encoding="user"
 480     - Many improvements in GreenPAK4 support
 481     - Added black box modules for all Xilinx 7-series lib cells
 482     - Added synth_ice40 support for latches via logic loops
 483     - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
 484
 485  * Build System
 486     - Added ABCEXTERNAL and ABCURL make variables
 487     - Added BINDIR, LIBDIR, and DATDIR make variables
 488     - Added PKG_CONFIG make variable
 489     - Added SEED make variable (for "make test")
 490     - Added YOSYS_VER_STR make variable
 491     - Updated min GCC requirement to GCC 4.8
 492     - Updated required Bison version to Bison 3.x
 493
 494  * Internal APIs
 495     - Added ast.h to exported headers
 496     - Added ScriptPass helper class for script-like passes
 497     - Added CellEdgesDatabase API
 498
 499  * Front-ends and Back-ends
 500     - Added filename glob support to all front-ends
 501     - Added avail (black-box) module params to ilang format
 502     - Added $display %m support
 503     - Added support for $stop Verilog system task
 504     - Added support for SystemVerilog packages
 505     - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
 506     - Added support for "active high" and "active low" latches in read_blif and write_blif
 507     - Use init value "2" for all uninitialized FFs in BLIF back-end
 508     - Added "read_blif -sop"
 509     - Added "write_blif -noalias"
 510     - Added various write_blif options for VTR support
 511     - write_json: also write module attributes.
 512     - Added "write_verilog -nodec -nostr -defparam"
 513     - Added "read_verilog -norestrict -assume-asserts"
 514     - Added support for bus interfaces to "read_liberty -lib"
 515     - Added liberty parser support for types within cell decls
 516     - Added "write_verilog -renameprefix -v"
 517     - Added "write_edif -nogndvcc"
 518
 519  * Formal Verification
 520     - Support for hierarchical designs in smt2 back-end
 521     - Yosys-smtbmc: Support for hierarchical VCD dumping
 522     - Added $initstate cell type and vlog function
 523     - Added $anyconst and $anyseq cell types and vlog functions
 524     - Added printing of code loc of failed asserts to yosys-smtbmc
 525     - Added memory_memx pass, "memory -memx", and "prep -memx"
 526     - Added "proc_mux -ifx"
 527     - Added "yosys-smtbmc -g"
 528     - Deprecated "write_smt2 -regs" (by default on now)
 529     - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
 530     - Added support for memories to smtio.py
 531     - Added "yosys-smtbmc --dump-vlogtb"
 532     - Added "yosys-smtbmc --smtc --dump-smtc"
 533     - Added "yosys-smtbmc --dump-all"
 534     - Added assertpmux command
 535     - Added "yosys-smtbmc --unroll"
 536     - Added $past, $stable, $rose, $fell SVA functions
 537     - Added "yosys-smtbmc --noinfo and --dummy"
 538     - Added "yosys-smtbmc --noincr"
 539     - Added "yosys-smtbmc --cex <filename>"
 540     - Added $ff and $_FF_ cell types
 541     - Added $global_clock verilog syntax support for creating $ff cells
 542     - Added clk2fflogic
 543
 544
 545 Yosys 0.5 .. Yosys 0.6
 546 ----------------------
 547
 548  * Various
 549      - Added Contributor Covenant Code of Conduct
 550      - Various improvements in dict<> and pool<>
 551      - Added hashlib::mfp and refactored SigMap
 552      - Improved support for reals as module parameters
 553      - Various improvements in SMT2 back-end
 554      - Added "keep_hierarchy" attribute
 555      - Verilog front-end: define `BLACKBOX in -lib mode
 556      - Added API for converting internal cells to AIGs
 557      - Added ENABLE_LIBYOSYS Makefile option
 558      - Removed "techmap -share_map" (use "-map +/filename" instead)
 559      - Switched all Python scripts to Python 3
 560      - Added support for $display()/$write() and $finish() to Verilog front-end
 561      - Added "yosys-smtbmc" formal verification flow
 562      - Added options for clang sanitizers to Makefile
 563
 564  * New commands and options
 565      - Added "scc -expect <N> -nofeedback"
 566      - Added "proc_dlatch"
 567      - Added "check"
 568      - Added "select %xe %cie %coe %M %C %R"
 569      - Added "sat -dump_json" (WaveJSON format)
 570      - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
 571      - Added "sat -stepsize" and "sat -tempinduct-step"
 572      - Added "sat -show-regs -show-public -show-all"
 573      - Added "write_json" (Native Yosys JSON format)
 574      - Added "write_blif -attr"
 575      - Added "dffinit"
 576      - Added "chparam"
 577      - Added "muxcover"
 578      - Added "pmuxtree"
 579      - Added memory_bram "make_outreg" feature
 580      - Added "splice -wires"
 581      - Added "dff2dffe -direct-match"
 582      - Added simplemap $lut support
 583      - Added "read_blif"
 584      - Added "opt_share -share_all"
 585      - Added "aigmap"
 586      - Added "write_smt2 -mem -regs -wires"
 587      - Added "memory -nordff"
 588      - Added "write_smv"
 589      - Added "synth -nordff -noalumacc"
 590      - Added "rename -top new_name"
 591      - Added "opt_const -clkinv"
 592      - Added "synth -nofsm"
 593      - Added "miter -assert"
 594      - Added "read_verilog -noautowire"
 595      - Added "read_verilog -nodpi"
 596      - Added "tribuf"
 597      - Added "lut2mux"
 598      - Added "nlutmap"
 599      - Added "qwp"
 600      - Added "test_cell -noeval"
 601      - Added "edgetypes"
 602      - Added "equiv_struct"
 603      - Added "equiv_purge"
 604      - Added "equiv_mark"
 605      - Added "equiv_add -try -cell"
 606      - Added "singleton"
 607      - Added "abc -g -luts"
 608      - Added "torder"
 609      - Added "write_blif -cname"
 610      - Added "submod -copy"
 611      - Added "dffsr2dff"
 612      - Added "stat -liberty"
 613
 614  * Synthesis metacommands
 615      - Various improvements in synth_xilinx
 616      - Added synth_ice40 and synth_greenpak4
 617      - Added "prep" metacommand for "synthesis lite"
 618
 619  * Cell library changes
 620      - Added cell types to "help" system
 621      - Added $meminit cell type
 622      - Added $assume cell type
 623      - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
 624      - Added $tribuf and $_TBUF_ cell types
 625      - Added read-enable to memory model
 626
 627  * YosysJS
 628      - Various improvements in emscripten build
 629      - Added alternative webworker-based JS API
 630      - Added a few example applications
 631
 632
 633 Yosys 0.4 .. Yosys 0.5
 634 ----------------------
 635
 636  * API changes
 637      - Added log_warning()
 638      - Added eval_select_args() and eval_select_op()
 639      - Added cell->known(), cell->input(portname), cell->output(portname)
 640      - Skip blackbox modules in design->selected_modules()
 641      - Replaced std::map<> and std::set<> with dict<> and pool<>
 642      - New SigSpec::extend() is what used to be SigSpec::extend_u0()
 643      - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
 644
 645  * Cell library changes
 646      - Added flip-flops with enable ($dffe etc.)
 647      - Added $equiv cells for equivalence checking framework
 648
 649  * Various
 650      - Updated ABC to hg rev 61ad5f908c03
 651      - Added clock domain partitioning to ABC pass
 652      - Improved plugin building (see "yosys-config --build")
 653      - Added ENABLE_NDEBUG Makefile flag for high-performance builds
 654      - Added "yosys -d", "yosys -L" and other driver improvements
 655      - Added support for multi-bit (array) cell ports to "write_edif"
 656      - Now printing most output to stdout, not stderr
 657      - Added "onehot" attribute (set by "fsm_map")
 658      - Various performance improvements
 659      - Vastly improved Xilinx flow
 660      - Added "make unsintall"
 661
 662  * Equivalence checking
 663      - Added equivalence checking commands:
 664          equiv_make equiv_simple equiv_status
 665          equiv_induct equiv_miter
 666          equiv_add equiv_remove
 667
 668  * Block RAM support:
 669      - Added "memory_bram" command
 670      - Added BRAM support to Xilinx flow
 671
 672  * Other New Commands and Options
 673      - Added "dff2dffe"
 674      - Added "fsm -encfile"
 675      - Added "dfflibmap -prepare"
 676      - Added "write_blid -unbuf -undef -blackbox"
 677      - Added "write_smt2" for writing SMT-LIBv2 files
 678      - Added "test_cell -w -muxdiv"
 679      - Added "select -read"
 680
 681
 682 Yosys 0.3.0 .. Yosys 0.4
 683 ------------------------
 684
 685  * Platform Support
 686      - Added support for mxe-based cross-builds for win32
 687      - Added sourcecode-export as VisualStudio project
 688      - Added experimental EMCC (JavaScript) support
 689
 690  * Verilog Frontend
 691      - Added -sv option for SystemVerilog (and automatic *.sv file support)
 692      - Added support for real-valued constants and constant expressions
 693      - Added support for non-standard "via_celltype" attribute on task/func
 694      - Added support for non-standard "module mod_name(...);" syntax
 695      - Added support for non-standard """ macro bodies
 696      - Added support for array with more than one dimension
 697      - Added support for $readmemh and $readmemb
 698      - Added support for DPI functions
 699
 700  * Changes in internal cell library
 701      - Added $shift and $shiftx cell types
 702      - Added $alu, $lcu, $fa and $macc cell types
 703      - Removed $bu0 and $safe_pmux cell types
 704      - $mem/$memwr WR_EN input is now a per-data-bit enable signal
 705      - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
 706      - Renamed ports of $lut cells (from I->O to A->Y)
 707      - Renamed $_INV_ to $_NOT_
 708
 709  * Changes for simple synthesis flows
 710      - There is now a "synth" command with a recommended default script
 711      - Many improvements in synthesis of arithmetic functions to gates
 712          - Multipliers and adders with many operands are using carry-save adder trees
 713          - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
 714      - Various new high-level optimizations on RTL netlist
 715      - Various improvements in FSM optimization
 716      - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
 717
 718  * Changes in internal APIs and RTLIL
 719      - Added log_id() and log_cell() helper functions
 720      - Added function-like cell creation helpers
 721      - Added GetSize() function (like .size() but with int)
 722      - Major refactoring of RTLIL::Module and related classes
 723      - Major refactoring of RTLIL::SigSpec and related classes
 724      - Now RTLIL::IdString is essentially an int
 725      - Added macros for code coverage counters
 726      - Added some Makefile magic for pretty make logs
 727      - Added "kernel/yosys.h" with all the core definitions
 728      - Changed a lot of code from FILE* to c++ streams
 729      - Added RTLIL::Monitor API and "trace" command
 730      - Added "Yosys" C++ namespace
 731
 732  * Changes relevant to SAT solving
 733      - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
 734      - Added native ezSAT support for vector shift ops
 735      - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
 736
 737  * New commands (or large improvements to commands)
 738      - Added "synth" command with default script
 739      - Added "share" (finally some real resource sharing)
 740      - Added "memory_share" (reduce number of ports on memories)
 741      - Added "wreduce" and "alumacc" commands
 742      - Added "opt -keepdc -fine -full -fast"
 743      - Added some "test_*" commands
 744
 745  * Various other changes
 746      - Added %D and %c select operators
 747      - Added support for labels in yosys scripts
 748      - Added support for here-documents in yosys scripts
 749      - Support "+/" prefix for files from proc_share_dir
 750      - Added "autoidx" statement to ilang language
 751      - Switched from "yosys-svgviewer" to "xdot"
 752      - Renamed "stdcells.v" to "techmap.v"
 753      - Various bug fixes and small improvements
 754      - Improved welcome and bye messages
 755
 756
 757 Yosys 0.2.0 .. Yosys 0.3.0
 758 --------------------------
 759
 760  * Driver program and overall behavior:
 761      - Added "design -push" and "design -pop"
 762      - Added "tee" command for redirecting log output
 763
 764  * Changes in the internal cell library:
 765      - Added $dlatchsr and $_DLATCHSR_???_ cell types
 766
 767  * Improvements in Verilog frontend:
 768      - Improved support for const functions (case, always, repeat)
 769      - The generate..endgenerate keywords are now optional
 770      - Added support for arrays of module instances
 771      - Added support for "`default_nettype" directive
 772      - Added support for "`line" directive
 773
 774  * Other front- and back-ends:
 775      - Various changes to "write_blif" options
 776      - Various improvements in EDIF backend
 777      - Added "vhdl2verilog" pseudo-front-end
 778      - Added "verific" pseudo-front-end
 779
 780  * Improvements in technology mapping:
 781      - Added support for recursive techmap
 782      - Added CONSTMSK and CONSTVAL features to techmap
 783      - Added _TECHMAP_CONNMAP_*_ feature to techmap
 784      - Added _TECHMAP_REPLACE_ feature to techmap
 785      - Added "connwrappers" command for wrap-extract-unwrap method
 786      - Added "extract -map %<design_name>" feature
 787      - Added "extract -ignore_param ..." and "extract -ignore_parameters"
 788      - Added "techmap -max_iter" option
 789
 790  * Improvements to "eval" and "sat" framework:
 791      - Now include a copy of Minisat (with build fixes applied)
 792      - Switched to Minisat::SimpSolver as SAT back-end
 793      - Added "sat -dump_vcd" feature
 794      - Added "sat -dump_cnf" feature
 795      - Added "sat -initsteps <N>" feature
 796      - Added "freduce -stop <N>" feature
 797      - Added "freduce -dump <prefix>" feature
 798
 799  * Integration with ABC:
 800      - Updated ABC rev to 7600ffb9340c
 801
 802  * Improvements in the internal APIs:
 803      - Added RTLIL::Module::add... helper methods
 804      - Various build fixes for OSX (Darwin) and OpenBSD
 805
 806
 807 Yosys 0.1.0 .. Yosys 0.2.0
 808 --------------------------
 809
 810  * Changes to the driver program:
 811      - Added "yosys -h" and "yosys -H"
 812      - Added support for backslash line continuation in scripts
 813      - Added support for #-comments in same line as command
 814      - Added "echo" and "log" commands
 815
 816  * Improvements in Verilog frontend:
 817      - Added support for local registers in named blocks
 818      - Added support for "case" in "generate" blocks
 819      - Added support for $clog2 system function
 820      - Added support for basic SystemVerilog assert statements
 821      - Added preprocessor support for macro arguments
 822      - Added preprocessor support for `elsif statement
 823      - Added "verilog_defaults" command
 824      - Added read_verilog -icells option
 825      - Added support for constant sizes from parameters
 826      - Added "read_verilog -setattr"
 827      - Added support for function returning 'integer'
 828      - Added limited support for function calls in parameter values
 829      - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
 830
 831  * Other front- and back-ends:
 832      - Added BTOR backend
 833      - Added Liberty frontend
 834
 835  * Improvements in technology mapping:
 836      - The "dfflibmap" command now strongly prefers solutions with
 837            no inverters in clock paths
 838      - The "dfflibmap" command now prefers cells with smaller area
 839      - Added support for multiple -map options to techmap
 840      - Added "dfflibmap" support for //-comments in liberty files
 841      - Added "memory_unpack" command to revert "memory_collect"
 842      - Added standard techmap rule "techmap -share_map pmux2mux.v"
 843      - Added "iopadmap -bits"
 844      - Added "setundef" command
 845      - Added "hilomap" command
 846
 847  * Changes in the internal cell library:
 848      - Major rewrite of simlib.v for better compatibility with other tools
 849      - Added PRIORITY parameter to $memwr cells
 850      - Added TRANSPARENT parameter to $memrd cells
 851      - Added RD_TRANSPARENT parameter to $mem cells
 852      - Added $bu0 cell (always 0-extend, even undef MSB)
 853      - Added $assert cell type
 854      - Added $slice and $concat cell types
 855
 856  * Integration with ABC:
 857      - Updated ABC to hg rev 2058c8ccea68
 858      - Tighter integration of ABC build with Yosys build. The make
 859            targets 'make abc' and 'make install-abc' are now obsolete.
 860      - Added support for passing FFs from one clock domain through ABC
 861      - Now always use BLIF as exchange format with ABC
 862      - Added support for "abc -script +<command_sequence>"
 863      - Improved standard ABC recipe
 864      - Added support for "keep" attribute to abc command
 865      - Added "abc -dff / -clk / -keepff" options
 866
 867  * Improvements to "eval" and "sat" framework:
 868      - Added support for "0" and "~0" in right-hand side -set expressions
 869      - Added "eval -set-undef" and "eval -table"
 870      - Added "sat -set-init" and "sat -set-init-*" for sequential problems
 871      - Added undef support to SAT solver, incl. various new "sat" options
 872      - Added correct support for === and !== for "eval" and "sat"
 873      - Added "sat -tempinduct" (default -seq is now non-induction sequential)
 874      - Added "sat -prove-asserts"
 875      - Complete rewrite of the 'freduce' command
 876      - Added "miter" command
 877      - Added "sat -show-inputs" and "sat -show-outputs"
 878      - Added "sat -ignore_unknown_cells" (now produce an error by default)
 879      - Added "sat -falsify"
 880      - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
 881      - Added "expose" command
 882      - Added support for @<sel_name> to sat and eval signal expressions
 883
 884  * Changes in the 'make test' framework and auxiliary test tools:
 885      - Added autotest.sh -p and -f options
 886      - Replaced autotest.sh ISIM support with XSIM support
 887      - Added test cases for SAT framework
 888
 889  * Added "abbreviated IDs":
 890      - Now $<something>$foo can be abbreviated as $foo.
 891      - Usually this last part is a unique id (from RTLIL::autoidx)
 892      - This abbreviated IDs are now also used in "show" output
 893
 894  * Other changes to selection framework:
 895      - Now */ is optional in */<mode>:<arg> expressions
 896      - Added "select -assert-none" and "select -assert-any"
 897      - Added support for matching modules by attribute (A:<expr>)
 898      - Added "select -none"
 899      - Added support for r:<expr> pattern for matching cell parameters
 900      - Added support for !=, <, <=, >=, > for attribute and parameter matching
 901      - Added support for %s for selecting sub-modules
 902      - Added support for %m for expanding selections to whole modules
 903      - Added support for i:*, o:* and x:* pattern for selecting module ports
 904      - Added support for s:<expr> pattern for matching wire width
 905      - Added support for %a operation to select wire aliases
 906
 907  * Various other changes to commands and options:
 908      - The "ls" command now supports wildcards
 909      - Added "show -pause" and "show -format dot"
 910      - Added "show -color" support for cells
 911      - Added "show -label" and "show -notitle"
 912      - Added "dump -m" and "dump -n"
 913      - Added "history" command
 914      - Added "rename -hide"
 915      - Added "connect" command
 916      - Added "splitnets -driver"
 917      - Added "opt_const -mux_undef"
 918      - Added "opt_const -mux_bool"
 919      - Added "opt_const -undriven"
 920      - Added "opt -mux_undef -mux_bool -undriven -purge"
 921      - Added "hierarchy -libdir"
 922      - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
 923      - Added "delete" command
 924      - Added "dump -append"
 925      - Added "setattr" and "setparam" commands
 926      - Added "design -stash/-copy-from/-copy-to"
 927      - Added "copy" command
 928      - Added "splice" command
 929