CHANGES: add JTAG UART.
[litex.git] / CHANGES
1 [> 2020.XX, planned for July 2020
2 ---------------------------------
3
4 [> Issues resolved
5 ------------------
6 - Fix flush_cpu_icache on VexRiscv.
7
8 [> Added Features
9 ------------------
10 - JTAG UART with uart_name=jtag_uart (validated on Spartan6, 7-Series, Ultrascale(+)).
11 - Add CV32E40P CPU support (ex RI5CY).
12 - Use InterconnectPointToPoint when 1 master,1 slave and no address translation.
13 - Improve WishboneBridge.
14 - Improve Diamond constraints.
15 - Add LedChaser on boards.
16 - Speedup Memtest using an LFSR.
17 - Add Microwatt CPU support (with GHDL-Yosys-plugin support for FOSS toolchains).
18 - Improve boards's programmers.
19 - BIOS history, autocomplete.
20 - Pluggable CPUs.
21 - Add nMigen dependency.
22 - Properly integrate Minerva CPU.
23
24 [> API changes/Deprecation
25 --------------------------
26 - Add --build --load arguments to targets.
27
28
29 [> 2020.04, released April 28th, 2020
30 -------------------------------------
31
32 [> Description
33 --------------
34 First release of LiteX and the ecosystem of cores!
35
36 LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create
37 Cores/SoCs (with or without CPU).
38
39 The common components of a SoC are provided directly:
40 - Buses and Streams (Wishbone, AXI, Avalon-ST)
41 - Interconnect
42 - Common cores (RAM, ROM, Timer, UART, etc...)
43 - CPU wrappers/integration
44 - etc...
45 And SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM,
46 PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX.
47
48 It also provides build backends for open-source and vendors toolchains.
49
50 [> Issues resolved
51 ------------------
52 - NA
53
54 [> Added Features
55 ------------------
56 - NA
57
58 [> API changes/Deprecation
59 --------------------------
60 - https://github.com/enjoy-digital/litex/pull/399: Converting LiteX to use Python modules.