Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn

   1 # Comparative analysis with Andes Packed ISA proposal
   2
   3 ## Register file
   4
   5 The harmonised RVP register file is divided into a lower bank of Vector[INT8] and an upper bank of Vector[INT16]
   6
   7 | Register           | Andes ISA                              | Harmonised RVP ISA            |
   8 | ------------------ | -------------------------              | -------------------           |
   9 | v0                 | Hardwired zero                         | Hardwired zero                |
  10 | v1                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | Predicate masks               |
  11 | v2                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
  12 | v3                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
  13 | v4                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
  14 | v5                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
  15 | v6                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
  16 | v7                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
  17 | v8                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  18 | v9                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  19 | v10                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  20 | v11                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  21 | v12                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  22 | v13                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  23 | v14                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  24 | v15                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  25 | |  |  |
  26 | v16                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  27 | v17                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  28 | v18                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  29 | v19                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  30 | v20                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  31 | v21                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  32 | v22                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  33 | v23                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  34 | v24                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
  35 | v25                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
  36 | v26                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
  37 | v27                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
  38 | v28                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
  39 | v29                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
  40 | v30                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[1xSINT32] |
  41 | v31                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[1xSINT32] |
  42
  43
  44 ## 16-bit Arithmetic
  45
  46 | Andes Mnemonic           | 16-bit Instruction        | Harmonised RVP Equivalent |
  47 | ------------------ | ------------------------- | ------------------- |
  48 | ADD16 rt, ra, rb   | Add                       | VADD (r16 <= rt,ra,rb <= r29), mm=00|
  49 | RADD16 rt, ra, rb  | Signed Halving add        | RADD (r16 <= rt,ra,rb <= r23), mm=00|
  50 | URADD16 rt, ra, rb | Unsigned Halving add      | RADD (r24 <= rt,ra,rb <= r29), mm=00|
  51 | KADD16 rt, ra, rb  | Signed Saturating add     | VADD (r16 <= rt,ra,rb <= r23), mm=01|
  52 | UKADD16 rt, ra, rb | Unsigned Saturating add   | VADD (r24 <= rt,ra,rb <= r29), mm=01|
  53 | SUB16 rt, ra, rb   | Subtract                  | VSUB (r16 <= rt,ra,rb <= r29), mm=00|
  54 | RSUB16 rt, ra, rb  | Signed Halving sub        | RSUB (r16 <= rt,ra,rb <= r23), mm=00|
  55 | URSUB16 rt, ra, rb | Unsigned Halving sub                | RSUB (r24 <= rt,ra,rb <= r29), mm=00|
  56 | KSUB16 rt, ra, rb  | Signed Saturating sub               | VSUB (r16 <= rt,ra,rb <= r23), mm=01|
  57 | UKSUB16 rt, ra, rb | Unsigned Saturating sub             | VSUB (r24 <= rt,ra,rb <= r29), mm=01|
  58 | CRAS16 rt, ra, rb  | Cross Add & Sub                     | |
  59 | RCRAS16 rt, ra, rb | Signed Halving Cross Add & Sub      | |
  60 | URCRAS16 rt, ra, rb| Unsigned Halving Cross Add & Sub    | |
  61 | KCRAS16 rt, ra, rb | Signed Saturating Cross Add & Sub   | |
  62 | UKCRAS16 rt, ra, rb| Unsigned Saturating Cross Add & Sub | |
  63 | CRSA16 rt, ra, rb  | Cross Sub & Add                     | |
  64 | RCRSA16 rt, ra, rb | Signed Halving Cross Sub & Add      | |
  65 | URCRSA16 rt, ra, rb| Unsigned Halving Cross Sub & Add    | |
  66 | KCRSA16 rt, ra, rb | Signed Saturating Cross Sub & Add   | |
  67 | UKCRSA16 rt, ra, rb| Unsigned Saturating Cross Sub & Add | |
  68
  69 ## 8-bit Arithmetic
  70
  71 | Andes Mnemonic           | 8-bit Instruction        | Harmonised RVP Equivalent |
  72 | ------------------ | ------------------------- | ------------------- |
  73 | ADD8 rt, ra, rb    | Add                       | VADD (r2 <= rt,ra,rb <= r15), mm=00 |
  74 | RADD8 rt, ra, rb   | Signed Halving add        | RADD (r2 <= rt,ra,rb <= r7), mm=00 |
  75 | URADD8 rt, ra, rb  | Unsigned Halving add      | RADD (r8 <= rt,ra,rb <= r15), mm=00 |
  76 | KADD8 rt, ra, rb   | Signed Saturating add     | VADD (r2 <= rt,ra,rb <= r7), mm=01 |
  77 | UKADD8 rt, ra, rb  | Unsigned Saturating add   | VADD (r8 <= rt,ra,rb <= r15), mm=01 |
  78 | SUB8 rt, ra, rb    | Subtract                  | VSUB (r2 <= rt,ra,rb <= r15), mm=00 |
  79 | RSUB8 rt, ra, rb   | Signed Halving sub        | RSUB (r2 <= rt,ra,rb <= r7), mm=00 |
  80 | URSUB8 rt, ra, rb  | Unsigned Halving sub      | RSUB (r8 <= rt,ra,rb <= r15), mm=00 |
  81 | KSUB8 rt, ra, rb   | Signed Saturating sub        | VSUB (r2 <= rt,ra,rb <= r7), mm=01 |
  82 | UKSUB8 rt, ra, rb  | Unsigned Saturating sub      | VSUB (r8 <= rt,ra,rb <= r15), mm=01 |
  83
  84 ## 16-bit Shifts
  85
  86 SRA[I]16/SRL[I]16/SLL[I]16 to be mapped to VOP shift instructions in same manner as ADD16/SUB16
  87
  88 The “K” (Saturation) and “u” (Rounding) variants could be encoded using VOP’s mm field (mm=01 is saturated or rounded shift, mm=00 is standard VOP shift)
  89
  90 | Andes Mnemonic             | 16-bit Instruction         | Harmonised RVP Equivalent |
  91 | ------------------   | -------------------------  | ------------------- |
  92 | SRA16 rt, ra, rb     | Shift right arithmetic     | VSRA (r16 <= rt,ra,rb <= r29), mm=00|
  93 | SRAI16 rt, ra, im    | Shift right arithmetic imm | VSRAI (r16 <= rt,ra <= r29), mm=00|
  94 | SRA16.u rt, ra, rb   | Rounding Shift right arithmetic     | VSRA (r16 <= rt,ra,rb <= r29), mm=01|
  95 | SRAI16.u rt, ra, im  | Rounding Shift right arithmetic imm | VSRAI (r16 <= rt,ra <= r29), mm=01|
  96 | SRL16 rt, ra, rb     | Shift right logical        | VSRL (r16 <= rt,ra,rb <= r29), mm=00|
  97 | SRLI16 rt, ra, im    | Shift right logical imm    | VSRLI (r16 <= rt,ra <= r29), mm=00|
  98 | SRL16.u rt, ra, rb   | Rounding Shift right logical     | VSRL (r16 <= rt,ra,rb <= r29), mm=01|
  99 | SRLI16.u rt, ra, im  | Rounding Shift right logical imm | VSLRI (r16 <= rt,ra <= r29), mm=01|
 100 | SLL16 rt, ra, rb     | Shift left logical         | VSLL (r16 <= rt,ra,rb <= r29), mm=00|
 101 | SLLI16 rt, ra, im    | Shift left logical imm     | VSLLI (r16 <= rt,ra <= r29), mm=00|
 102 | KSLL16 rt, ra, rb    | Saturating Shift left logical       | VSLL (r16 <= rt,ra,rb <= r29), mm=01|
 103 | KSLLI16 rt, ra, im   | Saturating Shift left logical imm   | VSLLI (r16 <= rt,ra <= r29), mm=01|
 104 | KSLRA16 rt, ra, rb    | Saturating Shift left logical or Shift right arithmetic              ||
 105 | KSLRA16.u rt, ra, rb  | Saturating Shift left logical or Rounding Shift right arithmetic     ||
 106
 107
 108 ## 8-bit Shifts
 109
 110 Andes SIMD Packed ISA omits 8 bit shifts, but these can be encoded in Harmonised RVP as follows:
 111
 112 | Andes Mnemonic             | 8-bit Instruction         | Harmonised RVP Equivalent |
 113 | ------------------   | -------------------------  | ------------------- |
 114 | n/a     | Shift right arithmetic     | VSRA (r2 <= rt,ra,rb <= r15), mm=00|
 115 | n/a     | Shift right arithmetic imm | VSRAI (r2 <= rt,ra <= r15), mm=00|
 116 | n/a     | Rounding Shift right arithmetic     | VSRA (r2 <= rt,ra,rb <= r15), mm=01|
 117 | n/a     | Rounding Shift right arithmetic imm | VSRAI (r2 <= rt,ra <= r15), mm=01|
 118 | n/a     | Shift right logical        | VSRL (r2 <= rt,ra,rb <= r15), mm=00|
 119 | n/a     | Shift right logical imm    | VSRLI (r2 <= rt,ra <= r15), mm=00|
 120 | n/a     | Rounding Shift right logical     | VSRL (r2 <= rt,ra,rb <= r15), mm=01|
 121 | n/a     | Rounding Shift right logical imm | VSLRI (r2 <= rt,ra <= r15), mm=01|
 122 | n/a     | Shift left logical         | VSLL (r2 <= rt,ra,rb <= r15), mm=00|
 123 | n/a     | Shift left logical imm     | VSLLI (r2 <= rt,ra <= r15), mm=00|
 124 | n/a     | Saturating Shift left logical       | VSLL (r2 <= rt,ra,rb <= r15), mm=01|
 125 | n/a     | Saturating Shift left logical imm   | VSLLI (r2 <= rt,ra <= r15), mm=01|
 126
 127 ## 16-bit Comparison instructions
 128
 129 | Andes Mnemonic           | 16-bit Instruction        | Harmonised RVP Equivalent |
 130 | ------------------   | ------------------------- | ------------------- |
 131 | CMPEQ16 rt, ra, rb   | Compare equal             | VSEQ (r16 <= rt,ra,rb <= r29), mm=00|
 132 | SCMPLT16 rt, ra, rb   | Signed Compare less than        | !VSGT (r16 <= rt,ra,rb <= r23), mm=00|
 133 | SCMPLE16 rt, ra, rb   | Signed Compare less or equal    | VSLE (r16 <= rt,ra,rb <= r23), mm=00|
 134 | UCMPLT16 rt, ra, rb   | Unsigned Compare less than      | !VSGT (r24 <= rt,ra,rb <= r29), mm=00|
 135 | UCMPLE16 rt, ra, rb   | Unsigned Compare less or equal  | VSLE (r24 <= rt,ra,rb <= r29), mm=00|
 136
 137 ## 8-bit Comparison instructions
 138
 139 | Andes Mnemonic           | 8-bit Instruction        | Harmonised RVP Equivalent |
 140 | ------------------   | ------------------------- | ------------------- |
 141 | CMPEQ8 rt, ra, rb   | Compare equal             | VSEQ (r2 <= rt,ra,rb <= r7), mm=00|
 142 | SCMPLT8 rt, ra, rb   | Signed Compare less than        | !VSGT (r2 <= rt,ra,rb <= r7), mm=00|
 143 | SCMPLE8 rt, ra, rb   | Signed Compare less or equal    | VSLE (r2 <= rt,ra,rb <= r7), mm=00|
 144 | UCMPLT8 rt, ra, rb   | Unsigned Compare less than      | !VSGT (r8 <= rt,ra,rb <= r15), mm=00|
 145 | UCMPLE8 rt, ra, rb   | Unsigned Compare less or equal  | VSLE (r8 <= rt,ra,rb <= r15), mm=00|
 146
 147 ## 16-bit Miscellaneous instructions
 148
 149 | Andes Mnemonic      | 16-bit Instruction                | Harmonised RVP Equivalent |
 150 | ------------------  | ------------------------          | ------------------- |
 151 | SMIN16 rt, ra, rb   | Signed minimum                    | VMIN (r16 <= rt,ra,rb <= r23), mm=00|
 152 | UMIN16 rt, ra, rb   | Unsigned minimum                  | VMIN (r24 <= rt,ra,rb <= r29), mm=00|
 153 | SMAX16 rt, ra, rb   | Signed maximum                    | VMAX (r16 <= rt,ra,rb <= r23), mm=00|
 154 | UMAX16 rt, ra, rb   | Unsigned maximum                  | VMAX (r24 <= rt,ra,rb <= r29), mm=00|
 155 | SCLIP16 rt, ra, rb  | Signed clip                       | ?VCLIP (r16 <= rt,ra,rb <= r23), mm=01|
 156 | UCLIP16 rt, ra, rb  | Unsigned clip                     | ?VCLIP (r24 <= rt,ra,rb <= r29), mm=01|
 157 | KMUL16 rt, ra, rb   | Signed multiply 16x16->16         | VMUL (r16 <= rt,ra,rb <= r23), mm=01|
 158 | KMULX16 rt, ra, rb  | Signed crossed multiply 16x16->16 | |
 159 | SMUL16 rt, ra, rb   | Signed multiply 16x16->32         | VMUL (30 <= rt <= 31, r16 <= ra,rb <= r23), mm=00|
 160 | SMULX16 rt, ra, rb  | Signed crossed multiply 16x16->32 | |
 161 | UMUL16 rt, ra, rb   | Signed multiply 16x16->32         | VMUL (30 <= rt <= 31, r24 <= ra,rb <= r31), mm=00|
 162 | UMULX16 rt, ra, rb  | Signed crossed multiply 16x16->32 | |
 163 | KABS16 rt, ra, rb   | Saturated absolute value          | VSGNX (r16 <= rt <= r29, r16 <= ra,rb <= r23, mm=01) |
 164
 165 ## 8-bit Miscellaneous instructions
 166
 167 | Andes Mnemonic           | 8-bit Instruction        | Harmonised RVP Equivalent |
 168 | ------------------   | ------------------------- | ------------------- |
 169 | SMIN8 rt, ra, rb   | Signed minimum           | VMIN (r2 <= rt,ra,rb <= r7), mm=00|
 170 | UMIN8 rt, ra, rb   | Unsigned minimum         | VMIN (r8 <= rt,ra,rb <= r15), mm=00|
 171 | SMAX8 rt, ra, rb   | Signed maximum           | VMAX (r2 <= rt,ra,rb <= r7), mm=00|
 172 | UMAX8 rt, ra, rb   | Unsigned maximum         | VMAX (r8 <= rt,ra,rb <= r15), mm=00|
 173 | KABS8 rt, ra, rb   | Saturated absolute value | VSGNX (r2 <= rt <= r15, r2 <= ra,rb <= r8, mm=01) |