Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn

   1 # Comparative analysis of Andes Packed ISA proposal vs RVP Harmonised (with RV Vector spec)
   2
   3 ## Proposed Harmonised RVP vector op instruction encoding
   4
   5 Register x 2 -> register operations:
   6
   7 | 31 30 29 28 27 26 | 25  | 24 23 22 21 20 | 19 18 17 16 15 | 14 | 13 12 | 11 10 9 8 7 | 6 5 4 3 2 1 0 |
   8 | ----------------- | --  | -------------- | -------------- | -- | ----- | ----------- | ------------- |
   9 | func_6            | 0   | rs2            | rs1            | 0  | mm    | rd1         | VOP opcode    |
  10
  11 Immediate + register -> register operations:
  12
  13 | 31 30 29 | 28 27 26 | 25  | 24 23 22 21 20 | 19 18 17 16 15 | 14 | 13 12 | 11 10 9 8 7 | 6 5 4 3 2 1 0 |
  14 | -------- | -------- | --  | -------------- | -------------- | -- | ----- | ----------- | ------------- |
  15 | func_3   | imm[7:5] | 1   | imm[4:0]       | rs1            | 0  | mm    | rd1         | VOP opcode    |
  16
  17 Register x 3 -> register operations:
  18
  19 | 31 30 29 28 27 | 26 25  | 24 23 22 21 20 | 19 18 17 16 15 | 14 | 13 12 | 11 10 9 8 7 | 6 5 4 3 2 1 0 |
  20 | ----------------------- | -------------- | -------------- | -- | ----- | ----------- | ------------- |
  21 | rs3            | func_2 | rs2            | rs1            | 1  | mm    | rd1         | VOP opcode    |
  22
  23 Values for mm field (bits 12:13 above):
  24
  25 * mm = 00 -> use current global saturation or rounding, no mask
  26 * mm = 00 -> force saturation or rounding for this instruction only
  27 * mm = 10 -> use v1 as predicate mask
  28 * mm = 11 -> use ~v1 as predicate mask
  29
  30 ## Register file
  31
  32 The default Harmonised RVP GPR register file is divided into a lower bank of Vector[INT8] and an upper bank of Vector[INT16].
  33 In contrast, the Andes Packed SIMD ISA permits any GPR to be used for either INT8 or INT16 vector operations
  34
  35 | Register           | Andes ISA                              | Harmonised RVP ISA            |
  36 | ------------------ | -------------------------              | -------------------           |
  37 | v0                 | Hardwired zero                         | Hardwired zero                |
  38 | v1                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | Predicate mask                |
  39 | |  |  |
  40 | v2                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
  41 | v3                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
  42 | v4                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
  43 | v5                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
  44 | v6                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
  45 | v7                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
  46 | v8                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  47 | v9                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  48 | v10                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  49 | v11                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  50 | v12                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  51 | v13                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  52 | v14                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  53 | v15                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  54 | |  |  |
  55 | v16                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  56 | v17                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  57 | v18                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  58 | v19                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  59 | v20                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  60 | v21                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  61 | v22                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  62 | v23                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  63 | v24                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
  64 | v25                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
  65 | v26                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
  66 | v27                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
  67 | v28                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
  68 | v29                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
  69 | |  |  |
  70 | v30                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[1xSINT32] |
  71 | v31                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[1xSINT32] |
  72
  73
  74 ## 16-bit Arithmetic
  75
  76 | Andes Mnemonic           | 16-bit Instruction        | Harmonised RVP Equivalent |
  77 | ------------------ | ------------------------- | ------------------- |
  78 | ADD16 rt, ra, rb   | Add                       | VADD (v16 <= rt,ra,rb <= v29), mm=00|
  79 | RADD16 rt, ra, rb  | Signed Halving add        | RADD (v16 <= rt,ra,rb <= v23), mm=00|
  80 | URADD16 rt, ra, rb | Unsigned Halving add      | RADD (v24 <= rt,ra,rb <= v29), mm=00|
  81 | KADD16 rt, ra, rb  | Signed Saturating add     | VADD (v16 <= rt,ra,rb <= v23), mm=01|
  82 | UKADD16 rt, ra, rb | Unsigned Saturating add   | VADD (v24 <= rt,ra,rb <= v29), mm=01|
  83 | SUB16 rt, ra, rb   | Subtract                  | VSUB (v16 <= rt,ra,rb <= v29), mm=00|
  84 | RSUB16 rt, ra, rb  | Signed Halving sub        | RSUB (v16 <= rt,ra,rb <= v23), mm=00|
  85 | URSUB16 rt, ra, rb | Unsigned Halving sub                | RSUB (v24 <= rt,ra,rb <= v29), mm=00|
  86 | KSUB16 rt, ra, rb  | Signed Saturating sub               | VSUB (v16 <= rt,ra,rb <= v23), mm=01|
  87 | UKSUB16 rt, ra, rb | Unsigned Saturating sub             | VSUB (v24 <= rt,ra,rb <= v29), mm=01|
  88 | CRAS16 rt, ra, rb  | Cross Add & Sub                     | |
  89 | RCRAS16 rt, ra, rb | Signed Halving Cross Add & Sub      | |
  90 | URCRAS16 rt, ra, rb| Unsigned Halving Cross Add & Sub    | |
  91 | KCRAS16 rt, ra, rb | Signed Saturating Cross Add & Sub   | |
  92 | UKCRAS16 rt, ra, rb| Unsigned Saturating Cross Add & Sub | |
  93 | CRSA16 rt, ra, rb  | Cross Sub & Add                     | |
  94 | RCRSA16 rt, ra, rb | Signed Halving Cross Sub & Add      | |
  95 | URCRSA16 rt, ra, rb| Unsigned Halving Cross Sub & Add    | |
  96 | KCRSA16 rt, ra, rb | Signed Saturating Cross Sub & Add   | |
  97 | UKCRSA16 rt, ra, rb| Unsigned Saturating Cross Sub & Add | |
  98
  99 ## 8-bit Arithmetic
 100
 101 | Andes Mnemonic           | 8-bit Instruction        | Harmonised RVP Equivalent |
 102 | ------------------ | ------------------------- | ------------------- |
 103 | ADD8 rt, ra, rb    | Add                       | VADD (v2 <= rt,ra,rb <= v15), mm=00 |
 104 | RADD8 rt, ra, rb   | Signed Halving add        | RADD (v2 <= rt,ra,rb <= v7), mm=00 |
 105 | URADD8 rt, ra, rb  | Unsigned Halving add      | RADD (v8 <= rt,ra,rb <= v15), mm=00 |
 106 | KADD8 rt, ra, rb   | Signed Saturating add     | VADD (v2 <= rt,ra,rb <= v7), mm=01 |
 107 | UKADD8 rt, ra, rb  | Unsigned Saturating add   | VADD (v8 <= rt,ra,rb <= v15), mm=01 |
 108 | SUB8 rt, ra, rb    | Subtract                  | VSUB (v2 <= rt,ra,rb <= v15), mm=00 |
 109 | RSUB8 rt, ra, rb   | Signed Halving sub        | RSUB (v2 <= rt,ra,rb <= v7), mm=00 |
 110 | URSUB8 rt, ra, rb  | Unsigned Halving sub      | RSUB (v8 <= rt,ra,rb <= v15), mm=00 |
 111 | KSUB8 rt, ra, rb   | Signed Saturating sub        | VSUB (v2 <= rt,ra,rb <= v7), mm=01 |
 112 | UKSUB8 rt, ra, rb  | Unsigned Saturating sub      | VSUB (v8 <= rt,ra,rb <= v15), mm=01 |
 113
 114 ## 16-bit Shifts
 115
 116 SRA[I]16/SRL[I]16/SLL[I]16 to be mapped to VOP shift instructions in same manner as ADD16/SUB16
 117
 118 The “K” (Saturation) and “u” (Rounding) variants could be encoded using VOP’s mm field (mm=01 is saturated or rounded shift, mm=00 is standard VOP shift)
 119
 120 | Andes Mnemonic             | 16-bit Instruction         | Harmonised RVP Equivalent |
 121 | ------------------   | -------------------------  | ------------------- |
 122 | SRA16 rt, ra, rb     | Shift right arithmetic     | VSRA (v16 <= rt,ra,rb <= v29), mm=00|
 123 | SRAI16 rt, ra, im    | Shift right arithmetic imm | VSRAI (v16 <= rt,ra <= v29), mm=00|
 124 | SRA16.u rt, ra, rb   | Rounding Shift right arithmetic     | VSRA (v16 <= rt,ra,rb <= v29), mm=01|
 125 | SRAI16.u rt, ra, im  | Rounding Shift right arithmetic imm | VSRAI (v16 <= rt,ra <= v29), mm=01|
 126 | SRL16 rt, ra, rb     | Shift right logical        | VSRL (v16 <= rt,ra,rb <= v29), mm=00|
 127 | SRLI16 rt, ra, im    | Shift right logical imm    | VSRLI (v16 <= rt,ra <= v29), mm=00|
 128 | SRL16.u rt, ra, rb   | Rounding Shift right logical     | VSRL (v16 <= rt,ra,rb <= v29), mm=01|
 129 | SRLI16.u rt, ra, im  | Rounding Shift right logical imm | VSLRI (v16 <= rt,ra <= v29), mm=01|
 130 | SLL16 rt, ra, rb     | Shift left logical         | VSLL (v16 <= rt,ra,rb <= v29), mm=00|
 131 | SLLI16 rt, ra, im    | Shift left logical imm     | VSLLI (v16 <= rt,ra <= v29), mm=00|
 132 | KSLL16 rt, ra, rb    | Saturating Shift left logical       | VSLL (v16 <= rt,ra,rb <= v29), mm=01|
 133 | KSLLI16 rt, ra, im   | Saturating Shift left logical imm   | VSLLI (v16 <= rt,ra <= v29), mm=01|
 134 | KSLRA16 rt, ra, rb    | Saturating Shift left logical or Shift right arithmetic              ||
 135 | KSLRA16.u rt, ra, rb  | Saturating Shift left logical or Rounding Shift right arithmetic     ||
 136
 137
 138 ## 8-bit Shifts
 139
 140 Andes SIMD Packed ISA omits 8 bit shifts, but these can be encoded in Harmonised RVP as follows:
 141
 142 | Andes Mnemonic             | 8-bit Instruction         | Harmonised RVP Equivalent |
 143 | ------------------   | -------------------------  | ------------------- |
 144 | n/a     | Shift right arithmetic     | VSRA (v2 <= rt,ra,rb <= v15), mm=00|
 145 | n/a     | Shift right arithmetic imm | VSRAI (v2 <= rt,ra <= v15), mm=00|
 146 | n/a     | Rounding Shift right arithmetic     | VSRA (v2 <= rt,ra,rb <= v15), mm=01|
 147 | n/a     | Rounding Shift right arithmetic imm | VSRAI (v2 <= rt,ra <= v15), mm=01|
 148 | n/a     | Shift right logical        | VSRL (v2 <= rt,ra,rb <= v15), mm=00|
 149 | n/a     | Shift right logical imm    | VSRLI (v2 <= rt,ra <= v15), mm=00|
 150 | n/a     | Rounding Shift right logical     | VSRL (v2 <= rt,ra,rb <= v15), mm=01|
 151 | n/a     | Rounding Shift right logical imm | VSLRI (v2 <= rt,ra <= v15), mm=01|
 152 | n/a     | Shift left logical         | VSLL (v2 <= rt,ra,rb <= v15), mm=00|
 153 | n/a     | Shift left logical imm     | VSLLI (v2 <= rt,ra <= v15), mm=00|
 154 | n/a     | Saturating Shift left logical       | VSLL (v2 <= rt,ra,rb <= v15), mm=01|
 155 | n/a     | Saturating Shift left logical imm   | VSLLI (v2 <= rt,ra <= v15), mm=01|
 156
 157 ## 16-bit Comparison instructions
 158
 159 | Andes Mnemonic           | 16-bit Instruction        | Harmonised RVP Equivalent |
 160 | ------------------   | ------------------------- | ------------------- |
 161 | CMPEQ16 rt, ra, rb   | Compare equal             | VSEQ (v16 <= rt,ra,rb <= v29), mm=00|
 162 | SCMPLT16 rt, ra, rb   | Signed Compare less than        | !VSGT (v16 <= rt,ra,rb <= v23), mm=00|
 163 | SCMPLE16 rt, ra, rb   | Signed Compare less or equal    | VSLE (v16 <= rt,ra,rb <= v23), mm=00|
 164 | UCMPLT16 rt, ra, rb   | Unsigned Compare less than      | !VSGT (v24 <= rt,ra,rb <= v29), mm=00|
 165 | UCMPLE16 rt, ra, rb   | Unsigned Compare less or equal  | VSLE (v24 <= rt,ra,rb <= v29), mm=00|
 166
 167 ## 8-bit Comparison instructions
 168
 169 | Andes Mnemonic           | 8-bit Instruction        | Harmonised RVP Equivalent |
 170 | ------------------   | ------------------------- | ------------------- |
 171 | CMPEQ8 rt, ra, rb   | Compare equal             | VSEQ (v2 <= rt,ra,rb <= v7), mm=00|
 172 | SCMPLT8 rt, ra, rb   | Signed Compare less than        | !VSGT (v2 <= rt,ra,rb <= v7), mm=00|
 173 | SCMPLE8 rt, ra, rb   | Signed Compare less or equal    | VSLE (v2 <= rt,ra,rb <= v7), mm=00|
 174 | UCMPLT8 rt, ra, rb   | Unsigned Compare less than      | !VSGT (v8 <= rt,ra,rb <= v15), mm=00|
 175 | UCMPLE8 rt, ra, rb   | Unsigned Compare less or equal  | VSLE (v8 <= rt,ra,rb <= v15), mm=00|
 176
 177 ## 16-bit Miscellaneous instructions
 178
 179 | Andes Mnemonic      | 16-bit Instruction                | Harmonised RVP Equivalent |
 180 | ------------------  | ------------------------          | ------------------- |
 181 | SMIN16 rt, ra, rb   | Signed minimum                    | VMIN (v16 <= rt,ra,rb <= v23), mm=00|
 182 | UMIN16 rt, ra, rb   | Unsigned minimum                  | VMIN (v24 <= rt,ra,rb <= v29), mm=00|
 183 | SMAX16 rt, ra, rb   | Signed maximum                    | VMAX (v16 <= rt,ra,rb <= v23), mm=00|
 184 | UMAX16 rt, ra, rb   | Unsigned maximum                  | VMAX (v24 <= rt,ra,rb <= v29), mm=00|
 185 | SCLIP16 rt, ra, im  | Signed clip                       | ?VCLIP (v16 <= rt,ra,rb <= v23), mm=01|
 186 | UCLIP16 rt, ra, im  | Unsigned clip                     | ?VCLIP (v24 <= rt,ra,rb <= v29), mm=01|
 187 | KMUL16 rt, ra, rb   | Signed multiply 16x16->16         | VMUL (v16 <= rt,ra,rb <= v23), mm=01|
 188 | KMULX16 rt, ra, rb  | Signed crossed multiply 16x16->16 | |
 189 | SMUL16 rt, ra, rb   | Signed multiply 16x16->32         | VMUL (30 <= rt <= 31, v16 <= ra,rb <= v23), mm=00|
 190 | SMULX16 rt, ra, rb  | Signed crossed multiply 16x16->32 | |
 191 | UMUL16 rt, ra, rb   | Signed multiply 16x16->32         | VMUL (30 <= rt <= 31, v24 <= ra,rb <= r31), mm=00|
 192 | UMULX16 rt, ra, rb  | Signed crossed multiply 16x16->32 | |
 193 | KABS16 rt, ra       | Saturated absolute value          | VSGNX (v16 <= rt <= v29, v16 <= ra,rb <= v23, mm=01) |
 194
 195 ## 8-bit Miscellaneous instructions
 196
 197 | Andes Mnemonic           | 8-bit Instruction        | Harmonised RVP Equivalent |
 198 | ------------------   | ------------------------- | ------------------- |
 199 | SMIN8 rt, ra, rb   | Signed minimum           | VMIN (v2 <= rt,ra,rb <= v7), mm=00|
 200 | UMIN8 rt, ra, rb   | Unsigned minimum         | VMIN (v8 <= rt,ra,rb <= v15), mm=00|
 201 | SMAX8 rt, ra, rb   | Signed maximum           | VMAX (v2 <= rt,ra,rb <= v7), mm=00|
 202 | UMAX8 rt, ra, rb   | Unsigned maximum         | VMAX (v8 <= rt,ra,rb <= v15), mm=00|
 203 | KABS8 rt, ra       | Saturated absolute value | VSGNX (v2 <= rt <= v15, v2 <= ra,rb <= v8, mm=01) |
 204
 205 ## 8-bit Unpacking instructions
 206
 207 | Andes Mnemonic           | 8-bit Instruction       | Harmonised RVP Equivalent |
 208 | ------------------   | -------------------------   | ------------------- |
 209 | SUNPKD810 rt, ra     | Signed unpack bytes 1 & 0   | VMV (v16<= rt <= 23, v2 <= ra <= v7), mm=00|
 210 | SUNPKD820 rt, ra     | Signed unpack bytes 2 & 0   | |
 211 | SUNPKD830 rt, ra     | Signed unpack bytes 3 & 0   | |
 212 | SUNPKD831 rt, ra     | Signed unpack bytes 3 & 1   | |
 213 | ZUNPKD810 rt, ra     | Unsigned unpack bytes 1 & 0 | VMV (v24<= rt <= 31, v8 <= ra <= v15), mm=00|
 214 | ZUNPKD820 rt, ra     | Unsigned unpack bytes 2 & 0 | |
 215 | ZUNPKD830 rt, ra     | Unsigned unpack bytes 3 & 0 | |
 216 | ZUNPKD831 rt, ra     | Unsigned unpack bytes 3 & 1 | |