HDL_workflow/ECP5_FPGA.mdwn

   1 # ULX3S JTAG Connection with ft232r
   2
   3 Cross referenced with:
   4
   5 <https://bugs.libre-soc.org/show_bug.cgi?id=517>
   6
   7 <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/000873.html>
   8
   9 ## Original Instructions
  10
  11 See <https://bugs.libre-soc.org/show_bug.cgi?id=517#c0>
  12
  13 Checklist based on above
  14
  15 * For god's sake make sure you get this right, ***TRIPLE*** check everything.
  16
  17 * ***DO*** make sure to ***only*** drive an input as an input, and to ***only*** drive an output as an output.
  18
  19 * ***DO*** make sure to ***only*** wire up GND to GND with the jumper-cables.
  20
  21 * ***DO*** make sure that ***before*** even ***thinking*** of uploading to and powering up the FPGA that everything has been ***THOROUGHLY*** triple-checked.
  22
  23 If you violate any of the above stated hard-and-fast rules you will end up learning the hard way by **DESTROYING** the FPGA.
  24
  25 To start we have to ensure we have a safe set up.
  26
  27 | Checklist Step |
  28 |----------------|
  29 | Ensure power is disconnected from FPGA |
  30 | Ensure ft232r USB is disconnected |
  31 | Ensure FPGA USB is disconnected |
  32
  33 Now lets review all of the relevant material on this page before we begin the wiring process.
  34
  35 | Checklist Step |
  36 |----------------|
  37 | Review the ft232r Connector diagram and table |
  38 | Review the connections table for your model of fpga |
  39 | Ensure the orientation of the FPGA and ft232r match that of the images and diagrams on this page |
  40
  41 Next we will wire up the ft232r and our FPGA in three separate stages.
  42
  43 * First we will attach one end of a ***MALE-TO-MALE (MTM)*** jumper cable to each necessary female header pin-hole on the ft232f.
  44
  45 * Then we will attach one end of a ***FEMALE-TO-FEMALE (FTF)*** cable to each male header pin on the FPGA.
  46
  47 * Finally, we will connect the wires from the ft232r to the wires from the FPGA by matching the colours of the wires.
  48
  49 This way you do not lose the connections when you want to disconnect and store the two devices. We are using FEMALE-TO-FEMALE jumper cables on the male header pins of the FPGA so that the wires do not randomly damage the bare PCB due to a short.
  50
  51 We will wire each of the pins on the the ft232r according to the diagrams, tables, and images on this page.
  52
  53 According to [https://www.sparkfun.com/datasheets/IC/FT232R_v104.pdf], page 8 - Table 1: pin 4 - VCCIO - should be supplied *by the FPGA*.
  54
  55 Therefore we will not attach any jumpers to the red VCC wire of the ft232r cable, nor the fpga.
  56
  57 |   Action   | Colour | Pin Name |
  58 |------------|--------|----------|
  59 | Attach MTM | Black  |   GND    |
  60 | Attach MTM | Brown  |   TMS    |
  61 | Attach MTM | Orange |   TCK    |
  62 | Attach MTM | Yellow |   TDI    |
  63 | Attach MTM | Green  |   TDO    |
  64
  65 Next, we will wire each of the pins on the the FPGA according to the diagrams, tables, and images on this page.
  66
  67 Follow this section if you have the ULX3S FPGA:
  68
  69 |   Action   | Colour | Pin # | Pin Name |
  70 |------------|--------|-------|----------|
  71 | Attach FTF | Black  |   4   |   GND    |
  72 | Attach FTF | Yellow |   5   |   TDI    |
  73 | Attach FTF | Brown  |   6   |   TMS    |
  74 | Attach FTF | Orange |   7   |   TCK    |
  75 | Attach FTF | Green  |   8   |   TDO    |
  76
  77 Follow this section if you have the Versa ECP5 FPGA:
  78
  79 |   Action   | Colour | X3 Pin # | Pin Name |
  80 |------------|--------|----------|----------|
  81 | Attach FTF | Black  |     1    |   GND    |
  82 | Attach FTF | Yellow |     4    |   TDI    |
  83 | Attach FTF | Brown  |     5    |   TMS    |
  84 | Attach FTF | Orange |     6    |   TCK    |
  85 | Attach FTF | Green  |     7    |   TDO    |
  86
  87 Final steps for both FPGA boards:
  88
  89 | Checklist Step |
  90 |----------------|
  91 | Check each jumper wire connection between the corresponding pins on the FPGA and the ft232r **THREE** times |
  92
  93 Finally, we will connect the jumper cables of the same colour from ft232r and the FPGA.
  94
  95 | Checklist Step |
  96 |----------------|
  97 | Attach the ends of the **BLACK** jumper cables  |
  98 | Attach the ends of the **YELLOW** jumper cables |
  99 | Attach the ends of the **BROWN** jumper cables  |
 100 | Attach the ends of the **ORANGE** jumper cables |
 101 | Attach the ends of the **GREEN** jumper cables  |
 102
 103 Finally, plug in the USB end of the USB-to-MicroUSB cable that is plugged into the ft232r into your computer. Begin testing the SOC on the FPGA (instructions to follow).
 104
 105 ## Connecting the dots:
 106
 107 Accurate render of board for reference <https://github.com/emard/ulx3s/blob/master/pic/ulx3st.jpg>
 108
 109 Litex platform file <https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/ulx3s.py>
 110
 111     ("gpio", 0,
 112         Subsignal"p", Pins("B11")),
 113         Subsignal("n", Pins("C11")),
 114         IOStandard("LVCMOS33")
 115     ),
 116     ("gpio", 1,
 117         Subsignal("p", Pins("A10")),
 118         Subsignal("n", Pins("A11")),
 119         IOStandard("LVCMOS33")
 120     ),
 121
 122 ULX3S FPGA constraints file <https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf#L341-342>
 123
 124     LOCATE COMP "gp[0]" SITE "B11"; # J1_5+  GP0 PCLK
 125     LOCATE COMP "gn[0]" SITE "C11"; # J1_5-  GN0 PCLK
 126     LOCATE COMP "gp[1]" SITE "A10"; # J1_7+  GP1 PCLK
 127     LOCATE COMP "gn[1]" SITE "A11"; # J1_7-  GN1 PCLK
 128
 129 ULX3S FPGA Schematic <https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf>
 130
 131 ```
 132 J1 J2 PIN number 1-40 is for FEMALE 90° ANGLED header.
 133 For MALE VERTICAL header, SWAP EVEN and ODD pin numbers.
 134
 135                     J1
 136
 137  Label     [GP{x}]|PCB pin label|[GN{x}] Label
 138              (Pin count +)(Pin count -)
 139 ___________________V__________V________________
 140 NOT CONNECTED 3V3  2  |3.3V|  1  NOT CONNECTED
 141              [GND] 4  | -| |  3  NOT CONNECTED
 142 PCLKT0_0     [GP0] 6  |  0 |  5  [GN0] PCLKC0_0
 143 PCLKT0_1     [GP1] 8  |  1 |  7  [GN1] PCLKC0_1
 144
 145
 146 GP,GN 0-7 single-ended connected to Bank0
 147 GP,GN 8-13 differential bidirectional connected to BANK7
 148 ```
 149
 150 Connecting all the dots:
 151
 152 ```
 153 Board pin # (count) | Board pin label # | FPGA IO PAD | GPIO # (n/p) |   Label  |
 154       5 (J1_5-)     |         0         |      C11    |    gn[0]     | PCLKC0_0 |
 155       6 (J1_5+)     |         0         |      B11    |    gp[0]     | PCLKT0_0 |
 156       7 (J1_7-)     |         1         |      A11    |    gn[1]     | PCLKC0_1 |
 157       8 (J1_7+)     |         1         |      A10    |    gp[1]     | PCLKT0_1 |
 158 ```
 159
 160 As noted in the schematic pins GP,GN 0-7 are single ended non-differential pairs, whereas pins GP,GN 8-13 I haven't mapped out here as they are bidirectional differential pairs.
 161
 162 ft232 pin and wire colour table converted to jtag signal names:
 163
 164 ```
 165  _________________________
 166 | Pin # | Name |  Colour  |
 167 |-------|------|----------|
 168 |   1   | GND  |  Black   |
 169 |   2   | TMS  |  Brown   |
 170 |   4   | TCK  |  Orange  |
 171 |   5   | TDI  |  Yellow  |
 172 |   6   | TDO  |  Green   |
 173 |_______|______|__________|
 174 ```
 175
 176 Proposed FPGA External Pin to ft232r JTAG pin connections:
 177
 178 ```
 179    all pin #'s have headers pins on the fpga unless denoted as (no header)
 180  ______________________________________________________________________________
 181 |             | board |             |             |                |           |
 182 |             | label |             |             | ft232r   JTAG  |           |
 183 |    pin #    |   #   | FPGA IO PAD |GPIO # (n/p) | Pin #  (Signal)|Wire Colour|
 184 |_____________|_______|_____________|_____________|________________|___________|
 185 |1 (no header)|  3.3v |NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
 186 |2            |  3.3v | IO VOLT REF | IO VOLT REF | NOT CONNECTED  |    NOT    |
 187 |3 (no header)|-|(GND)|NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
 188 |4            |-|(GND)|    NONE     |     GND     |    1 (GND)     |   Black   |
 189 |5 (J1_5-)    |   0   |     C11     |    gn[0]    |    5 (TDI)     |   Yellow  |
 190 |6 (J1_5+)    |   0   |     B11     |    gp[0]    |    2 (TMS)     |   Brown   |
 191 |7 (J1_7-)    |   1   |     A11     |    gn[1]    |    4 (TCK)     |   Orange  |
 192 |8 (J1_7+)    |   1   |     A10     |    gp[1]    |    6 (TDO)     |   Green   |
 193 |_____________|_______|_____________|_____________|________________|___________|
 194 ```
 195
 196 Complete diagram:
 197
 198 ```
 199 Pins intentionally have no header or are not connected to the ft232 are marked
 200 and therefore have no value are marked with 'NOT'
 201
 202 (ft232r# JTAG) = (ft232r pin #   JTAG signal name)
 203
 204                              J1
 205             Wire                             Wire
 206            Colour [GP{x}]|PCB label|[GN{x}] Colour
 207 (ft232r# JTAG)   (Pin count +)(Pin count -)   (ft232r# JTAG)
 208  ______________________V__________V_______________________
 209 |                                                         |
 210 |NOT      NOT   [VREF] 2  |3.3V|  1   NOT   NOT     NOT   |
 211 |(1 GND) black   [GND] 4  | -| |  3   NOT   NOT     NOT   |
 212 |(2 TMS) brown   [GP0] 6  |  0 |  5  [GN0] yellow (5 TDI) |
 213 |(6 TDO) green   [GP1] 8  |  1 |  7  [GN1] orange (4 TCK) |
 214 |_________________________________________________________|
 215 ```
 216
 217 ## Images of wires on FPGA and on ft232r
 218
 219 Image of JTAG jumper wire connections on ULX3S FPGA side
 220
 221 [[!img HDL_workflow/ulx3s_fpga_jtag_wires.jpg size="500x" ]]
 222
 223 Image of JTAG jumper wire connections on ft232r side
 224
 225 [[!img HDL_workflow/ft232r_jtag_wires.jpg size="500x" ]]
 226
 227 # VERSA ECP5 Connections
 228
 229 Table of connections:
 230
 231 | X3  pin #   | FPGA IO PAD |  ft232r   |Wire Colour|
 232 |-------------|-------------|-----------|-----------|
 233 |    1 GND    |     GND     |  1 (GND)  |   Black   |
 234 |    4 IO29   |     B19     |  5 (TDI)  |   Yellow  |
 235 |    5 IO30   |     B12     |  2 (TMS)  |   Brown   |
 236 |    6 IO31   |     B9      |  4 (TCK)  |   Orange  |
 237 |    7 IO32   |     E6      |  6 (TDO)  |   Green   |
 238
 239 [[!img 2020-11-03_13-22.png size="900x" ]]
 240
 241 [[!img 2020-11-03_13-25.png size="900x" ]]
 242
 243 [[!img versa_ecp5_x3_connector.jpg size="900x" ]]