HDL_workflow/ECP5_FPGA.mdwn

   1 # ULX3S JTAG Connection with STLINKV2
   2
   3 Cross referenced with:
   4
   5 <https://bugs.libre-soc.org/show_bug.cgi?id=517>
   6
   7 <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/000873.html>
   8
   9 ## Original Instructions
  10
  11 See https://bugs.libre-soc.org/show_bug.cgi?id=517#c0
  12
  13 TODO checklist based on above
  14
  15 ## Connecting the dots:
  16
  17 Accurate render of board for reference <https://github.com/emard/ulx3s/blob/master/pic/ulx3st.jpg>
  18
  19 STLINKV2 Pins and JTAG signals schematic/user guide <https://www.st.com/resource/en/user_manual/dm00026748-stlinkv2-incircuit-debuggerprogrammer-for-stm8-and-stm32-stmicroelectronics.pdf>
  20
  21 Litex platform file <https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/ulx3s.py>
  22
  23     ("gpio", 0,
  24         Subsignal"p", Pins("B11")),
  25         Subsignal("n", Pins("C11")),
  26         IOStandard("LVCMOS33")
  27     ),
  28     ("gpio", 1,
  29         Subsignal("p", Pins("A10")),
  30         Subsignal("n", Pins("A11")),
  31         IOStandard("LVCMOS33")
  32     ),
  33
  34 ULX3S FPGA constraints file <https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf#L341-342>
  35
  36     LOCATE COMP "gp[0]" SITE "B11"; # J1_5+  GP0 PCLK
  37     LOCATE COMP "gn[0]" SITE "C11"; # J1_5-  GN0 PCLK
  38     LOCATE COMP "gp[1]" SITE "A10"; # J1_7+  GP1 PCLK
  39     LOCATE COMP "gn[1]" SITE "A11"; # J1_7-  GN1 PCLK
  40
  41 ULX3S FPGA Schematic <https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf>
  42
  43 ```
  44 J1 J2 PIN number 1-40 is for FEMALE 90° ANGLED header.
  45 For MALE VERTICAL header, SWAP EVEN and ODD pin numbers.
  46
  47                     J1
  48
  49  Label  [GP{x}]|PCB pin label|[GN{x}] Label
  50            (Pin count +)(Pin count -)
  51 _________________V__________V________________
  52  IO VOLT REF 3V3 2  |3.3V|  1  NOT CONNECTED
  53            [GND] 4  | -| |  3  NOT CONNECTED
  54 PCLKT0_0   [GP0] 6  |  0 |  5  [GN0] PCLKC0_0
  55 PCLKT0_1   [GP1] 8  |  1 |  7  [GN1] PCLKC0_1
  56
  57
  58 GP,GN 0-7 single-ended connected to Bank0
  59 GP,GN 8-13 differential bidirectional connected to BANK7
  60 ```
  61
  62 Connecting all the dots:
  63
  64 ```
  65 Board pin # (count) | Board pin label # | FPGA IO PAD | GPIO # (n/p) |   Label  |
  66       5 (J1_5-)     |         0         |      C11    |    gn[0]     | PCLKC0_0 |
  67       6 (J1_5+)     |         0         |      B11    |    gp[0]     | PCLKT0_0 |
  68       7 (J1_7-)     |         1         |      A11    |    gn[1]     | PCLKC0_1 |
  69       8 (J1_7+)     |         1         |      A10    |    gp[1]     | PCLKT0_1 |
  70 ```
  71
  72 As noted in the schematic pins GP,GN 0-7 are single ended non-differential pairs, whereas pins GP,GN 8-13 I haven't mapped out here as they are bidirectional differential pairs.
  73
  74 Proposed FPGA External Pin to STLINK JTAG pin connections:
  75
  76 ```
  77    all pin #'s have headers pins on the fpga unless denoted as (no header)
  78  ______________________________________________________________________________
  79 |             | board |             |             |                |           |
  80 |             | label |             |             |STLINKV2  JTAG  |           |
  81 |    pin #    |   #   | FPGA IO PAD |GPIO # (n/p) | Pin #  (Signal)|Wire Colour|
  82 |_____________|_______|_____________|_____________|________________|___________|
  83 |1 (no header)|  3.3v |NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
  84 |2            |  3.3v | IO VOLT REF | IO VOLT REF |    2 (MCU VDD) |    Red    |
  85 |3 (no header)|-|(GND)|NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
  86 |4            |-|(GND)|    NONE     |     GND     |    4 (GND)     |   Black   |
  87 |5 (J1_5-)    |   0   |     C11     |    gn[0]    |    5 (JTDI)    |   Green   |
  88 |6 (J1_5+)    |   0   |     B11     |    gp[0]    |    7 (JTMS)    |   Blue    |
  89 |7 (J1_7-)    |   1   |     A11     |    gn[1]    |    9 (JTCK)    |   White   |
  90 |8 (J1_7+)    |   1   |     A10     |    gp[1]    |   13 (JTDO)    |   Yellow  |
  91 |_____________|_______|_____________|_____________|________________|___________|
  92 ```
  93
  94 Complete diagram:
  95
  96 ```
  97 Pins intentionally have no header or are not connected to the STLINKVT are marked
  98 and therefore have no value are marked with 'NOT'
  99
 100 (ST# JTAG) = (STLINKV2 pin #   JTAG signal name)
 101
 102
 103                              J1
 104             Wire                             Wire
 105            Colour [GP{x}]|PCB label|[GN{x}] Colour
 106 (ST# JTAG)        (Pin count +)(Pin count -)      (ST# JTAG)
 107  ________________________V__________V_________________________
 108 |                                                             |
 109 |( 2 JVDD) red    [VREF] 2  |3.3V|  1   NOT   NOT    NOT      |
 110 |( 4 JGND) black   [GND] 4  | -| |  3   NOT   NOT    NOT      |
 111 |( 7 JTMS) blue    [GP0] 6  |  0 |  5  [GN0] green (5 JTDI)   |
 112 |(13 JTDO) yellow  [GP1] 8  |  1 |  7  [GN1] white (9 JTCK)   |
 113 |_____________________________________________________________|
 114 ```
 115
 116 ## Images of wires on FPGA and on STLINKV2
 117
 118 Image of JTAG jumper wire connections on ULX3S FPGA side
 119
 120 [[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]]
 121
 122 Image of JTAG jumper wire connections on STLINKV2 side
 123
 124 (same orientation as JTAG pinout documentation)
 125
 126 [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2_same_orientation_as_jtag.jpg size="250x" ]]
 127
 128 Image of JTAG jumper wire connections on STLINKV2 side
 129
 130 (opposite orientation as JTAG pinout documentation,
 131
 132 same orientation as 'ST' text on STLINKV2 device)
 133
 134 [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2_opposite_orientation_to_jtag.jpg size="x302" ]]
 135
 136 # STLinkV2 connector
 137
 138 [[!img 2020-11-03_14-08.png size="900x" ]]
 139
 140 [[!img 2020-11-03_14-09.png size="900x" ]]
 141
 142 # VERSA ECP5 Connections
 143
 144 Table of connections:
 145
 146 | X3  pin #   | FPGA IO PAD | STLinkv2       |Wire Colour|
 147 |-------------|-------------|----------------|-----------|
 148 |1 GND        | GND         | 4 (GND)        |   Black   |
 149 |2 NC         | NC          |  NC            |    NC     |
 150 |39 +3.3V     | 3.3V supply | 2 (MCU VDD)    |   Red     |
 151 |4 IO29       |  B19        |    5 (TDI)     |   Green   |
 152 |5 IO30       |  B12        |    7 (TMS)     |   Blue    |
 153 |6 IO31       |  B9         |    9 (TCK)     |   White   |
 154 |7 IO32       |  E6         |   13 (TDO)     |   Yellow  |
 155
 156 [[!img 2020-11-03_13-22.png size="900x" ]]
 157
 158 [[!img 2020-11-03_13-25.png size="900x" ]]
 159
 160 [[!img versa_ecp5_x3_connector.jpg size="900x" ]]