HDL_workflow/fpga.mdwn

   1 # ULX3S JTAG Connection with STLINKV2
   2
   3 Cross referenced with:
   4 https://bugs.libre-soc.org/show_bug.cgi?id=517
   5 http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/000873.html
   6
   7 ```lkcl
   8 the JTAG TAP interface on the *FPGA* is hard-coded silicon.
   9
  10 the JTAG TAP interface connected on the processor and soft-implemented
  11 *by* the FPGA is likely completely inaccessible until someone
  12 allocates pins to "jtag_tdi/tdo/tms/tck" in the litex config.
  13
  14 which means: someone's going to have to to through this file:
  15 https://github.com/enjoy-digital/litex/blob/master/litex/boards/platforms/ulx3s.py#L72
  16 (which defines the pin allocations)
  17
  18 and in this file do some Voodoo Magic on this file's TestSoC:
  19 https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/litex/florent/ulx3s85f.py;hb=HEAD
  20
  21 similar to these four lines:
  22 https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/litex/florent/ls180soc.py;h=4279effcffe2fbf15f877e9b2a1b76beab248dac;hb=HEAD#l460
  23
  24 but instead doing something like... err....
  25 gpio0_pads = platform.reqiest("gpio", 0) # because back in ulx3s.py
  26 there's gpio 0, 1, and 2
  27 self.comb += self.cpu.jtag_tck.eq(gpio0_pads.p) # because again back
  28 in that file there are 2 pins, one named "p", one named "n"
  29 self.comb += self.cpu.jtag_tms.eq(gpio0_pads.n) # etc.
  30
  31 and then request gpio1 for the other 2 pins
  32
  33 theeeen you'll need to go back to that ulx3s.py litex platform file,
  34 look up the pin names B11, C11, A10, A11, and find out what the hell
  35 they are, whether they're suitable for use.
  36
  37 if they are, then great! these are what you wire up the STLINKv2 to,
  38 according to what you decided to connect to just above.
  39
  40 but for god's sake do not get this wrong, such as driving an input as
  41 an output or vice-versa, or wiring up 5.0V to GND with those
  42 jumper-cables.
  43
  44 do *NOT* randomly upload and power up the ulx3s until this has been
  45 THOROUGHLY triple-checked.  or, you are entirely free to not bother
  46 and to end up learning the hard way by destroying the FPGA.
  47 ```
  48
  49 Connecting the dots:
  50
  51
  52 litex platform file litex-boards/litex_boards/platforms/ulx3s.py
  53 ```
  54 ("gpio", 0,
  55     Subsignal("p", Pins("B11")),
  56     Subsignal("n", Pins("C11")),
  57     IOStandard("LVCMOS33")
  58 ),
  59 ("gpio", 1,
  60     Subsignal("p", Pins("A10")),
  61     Subsignal("n", Pins("A11")),
  62     IOStandard("LVCMOS33")
  63 ),
  64 ```
  65
  66 ulx3s contstraints file github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf#L341-342
  67 ```
  68 LOCATE COMP "gp[0]" SITE "B11"; # J1_5+  GP0 PCLK
  69 LOCATE COMP "gn[0]" SITE "C11"; # J1_5-  GN0 PCLK
  70 LOCATE COMP "gp[1]" SITE "A10"; # J1_7+  GP1 PCLK
  71 LOCATE COMP "gn[1]" SITE "A11"; # J1_7-  GN1 PCLK
  72 ```
  73
  74 ULX3S FPGA Schematic https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf
  75
  76 ```
  77 J1 J2 PIN number 1-40 is for FEMALE 90° ANGLED header.
  78 For MALE VERTICAL header, SWAP EVEN and ODD pin numbers.
  79
  80                     J1
  81
  82  Label  [GP{x}]|PCB pin label|[GN{x}] Label
  83            (Pin count +)(Pin count -)
  84 _________________V__________V________________
  85  IO VOLT REF 3V3 2  |3.3V|  1  NOT CONNECTED
  86            [GND] 4  | -| |  3  NOT CONNECTED
  87 PCLKT0_0   [GP0] 6  |  0 |  5  [GN0] PCLKC0_0
  88 PCLKT0_1   [GP1] 8  |  1 |  7  [GN1] PCLKC0_1
  89
  90
  91 GP,GN 0-7 single-ended connected to Bank0
  92 GP,GN 8-13 differential bidirectional connected to BANK7
  93 ```
  94
  95 ``` Connecting all the dots
  96 Board pin # (count) | Board pin label # | FPGA IO PAD | GPIO # (n/p) |   Label  |
  97       5 (J1_5-)     |         0         |      C11    |    gn[0]     | PCLKC0_0 |
  98       6 (J1_5+)     |         0         |      B11    |    gp[0]     | PCLKT0_0 |
  99       7 (J1_7-)     |         1         |      A11    |    gn[1]     | PCLKC0_1 |
 100       8 (J1_7+)     |         1         |      A10    |    gp[1]     | PCLKT0_1 |
 101 ```
 102
 103 As noted in the schematic pins GP,GN 0-7 are single ended non-differential pairs, whereas pins GP,GN 8-13 I haven't mapped out here as they are bidirectional differential pairs.
 104
 105
 106 ```proposed FPGA External Pin to STLINK JTAG pin connections
 107    all pin #'s have headers pins on the fpga unless denoted as (no header)
 108  ______________________________________________________________________________
 109 |             | board |             |             |                |           |
 110 |             | label |             |             |STLINKV2  JTAG  |           |
 111 |    pin #    |   #   | FPGA IO PAD |GPIO # (n/p) | Pin #  (Signal)|Wire Colour|
 112 |_____________|_______|_____________|_____________|________________|___________|
 113 |1 (no header)|  3.3v |NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
 114 |2            |  3.3v | IO VOLT REF | IO VOLT REF |    2 (MCU VDD) |    Red    |
 115 |3 (no header)|-|(GND)|NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
 116 |4            |-|(GND)|    NONE     |     GND     |    4 (GND)     |   Black   |
 117 |5 (J1_5-)    |   0   |     C11     |    gn[0]    |    5 (JTDI)    |   Green   |
 118 |6 (J1_5+)    |   0   |     B11     |    gp[0]    |    7 (JTMS)    |   Blue    |
 119 |7 (J1_7-)    |   1   |     A11     |    gn[1]    |    9 (JTCK)    |   White   |
 120 |8 (J1_7+)    |   1   |     A10     |    gp[1]    |   13 (JTDO)    |   Yellow  |
 121 |_____________|_______|_____________|_____________|________________|___________|
 122 ```
 123
 124 ```complete diagram
 125
 126 Pins intentionally have no header or are not connected to the STLINKVT are marked
 127 and therefore have no value are marked with 'NOT'
 128
 129 (ST# JTAG) = (STLINKV2 pin #   JTAG signal name)
 130
 131
 132                              J1
 133             Wire                             Wire
 134            Colour [GP{x}]|PCB label|[GN{x}] Colour
 135 (ST# JTAG)        (Pin count +)(Pin count -)      (ST# JTAG)
 136  ________________________V__________V_________________________
 137 |                                                             |
 138 |( 2 JVDD) red    [VREF] 2  |3.3V|  1   NOT   NOT    NOT      |
 139 |( 4 JGND) black   [GND] 4  | -| |  3   NOT   NOT    NOT      |
 140 |( 7 JTMS) blue    [GP0] 6  |  0 |  5  [GN0] green (5 JTDI)   |
 141 |(13 JTDO) yellow  [GP1] 8  |  1 |  7  [GN1] white (9 JTCK)   |
 142 |_____________________________________________________________|
 143 ```
 144
 145 pic fpga                                     pic stlinkv2
 146
 147 Luke do the labels of PCLK[C|T]0_[0|1] and GR_PCLK0_[0|1] have any significance? Should we be using the CLK labeled pins specifically for JTAG or specifically avoid using them for JTAG?
 148
 149 Additionally, does the note in the schematic about needing to swap EVEN and ODD pin numbers if using MALE VERTICAL header instead of FEMALE 90° ANGLED header apply to us?
 150