Makefile

   1 ls1804k:
   2         ./ls180soc.py --build --platform=ls180sram4k --num-srams=2
   3         cp build/ls180sram4k/gateware/ls180sram4k.v ./ls180.v
   4         cp build/ls180sram4k/gateware/mem.init .
   5         cp build/ls180sram4k/gateware/mem_1.init .
   6         cp libresoc/libresoc.v .
   7         yosys -p 'read_verilog libresoc.v' \
   8           -p 'write_ilang libresoc_cvt.il'
   9         yosys -p 'read_verilog ls180.v' \
  10               -p 'read_verilog SPBlock_512W64B8W.v' \
  11           -p 'write_ilang ls180_cvt.il'
  12         yosys -p 'read_ilang ls180_cvt.il' \
  13           -p 'read_ilang libresoc_cvt.il' \
  14           -p 'write_ilang ls180.il'
  15
  16 ls180:
  17         ./ls180soc.py --build --platform=ls180 --num-srams=2
  18         cp build/ls180/gateware/ls180.v .
  19         cp build/ls180/gateware/mem.init .
  20         cp build/ls180/gateware/mem_1.init .
  21         cp libresoc/libresoc.v .
  22         yosys -p 'read_verilog libresoc.v' \
  23               -p 'read_verilog ls180.v' \
  24           -p 'write_verilog ls180_cvt.v'
  25         yosys -p 'read_verilog ls180.v' \
  26               -p 'read_verilog SPBlock_512W64B8W.v' \
  27           -p 'write_ilang ls180_cvt.il'
  28         yosys -p 'read_verilog libresoc.v' \
  29           -p 'write_ilang libresoc_cvt.il'
  30         yosys -p 'read_verilog ls180.v' \
  31               -p 'read_verilog SPBlock_512W64B8W.v' \
  32           -p 'write_ilang ls180_cvt.il'
  33         yosys -p 'read_ilang ls180_cvt.il' \
  34           -p 'read_ilang libresoc_cvt.il' \
  35           -p 'write_ilang ls180.il'
  36
  37 versaecp5:
  38          ./versa_ecp5.py --sys-clk-freq=55e6 --build
  39
  40 versaecp5load:
  41         ./versa_ecp5.py --sys-clk-freq=55e6 --load