3 in the soc directory, create the verilog file
4 "python issuer_verilog.py libresoc.v"
6 copy to libresoc/ directory
8 terminal 2: openocd -f openocd.cfg -c init -c 'svf idcode_test2.svf'
12 same thing: first build libresoc.v and copy it to the libresoc/ directory
14 ./versa_ecp5.py --sys-clk-freq=55e6 --build --yosys-nowidelut
15 ./versa_ecp5.py --sys-clk-freq=55e6 --load
19 export PATH=$PATH:/usr/local/symbiflow/bin/:/usr/local/symbiflow/vtr/bin/
20 ./versa_ecp5.py --sys-clk-freq=25e6 --build --fpga=artya7100t \
22 ./versa_ecp5.py --sys-clk-freq=25e6 --load --fpga=artya7100t \