TLB/src/CamEntry.py

   1 from nmigen import Module, Signal
   2
   3 class CamEntry:
   4     """ Content Addressable Memory (CAM) Entry
   5
   6         The purpose of this module is to represent an entry within a CAM.
   7         This module when given a read command will compare  the given data
   8         and output whether a match was found or not. When given a write
   9         command it will write the given data into internal registers.
  10     """
  11
  12     def __init__(self, data_size):
  13         """ Arguments:
  14             * data_size: (bit count) The size of the data
  15         """
  16         # Input
  17         self.command = Signal(2) # 00 => NA 01 => Read 10 => Write 11 => Reset
  18         self.data_in = Signal(data_size) # Data input when writing
  19
  20         # Output
  21         self.match = Signal(1) # Result of the internal/input key comparison
  22         self.data = Signal(data_size)
  23
  24     def elaborate(self, platform=None):
  25         m = Module()
  26         with m.Switch(self.command):
  27             with m.Case("00"):
  28                 m.d.sync += self.match.eq(0)
  29             with m.Case("01"):
  30                 with m.If(self.data == self.data_in):
  31                     m.d.sync += self.match.eq(1)
  32                 with m.Else():
  33                     m.d.sync += self.match.eq(0)
  34             with m.Case("10"):
  35                 m.d.sync += [
  36                     self.data.eq(self.data_in),
  37                     self.match.eq(0)
  38                 ]
  39             with m.Case():
  40                 m.d.sync += [
  41                     self.match.eq(0),
  42                     self.data.eq(0)
  43                 ]
  44
  45         return m