cache_ram.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use ieee.math_real.all;
   5
   6 entity cache_ram is
   7     generic(
   8         ROW_BITS : integer := 16;
   9         WIDTH    : integer := 64
  10         );
  11
  12     port(
  13         clk     : in  std_logic;
  14         rd_en   : in  std_logic;
  15         rd_addr : in  std_logic_vector(ROW_BITS - 1 downto 0);
  16         rd_data : out std_logic_vector(WIDTH - 1 downto 0);
  17         wr_en   : in  std_logic;
  18         wr_addr : in  std_logic_vector(ROW_BITS - 1 downto 0);
  19         wr_data : in  std_logic_vector(WIDTH - 1 downto 0)
  20         );
  21
  22 end cache_ram;
  23
  24 architecture rtl of cache_ram is
  25     constant SIZE : integer := 2**ROW_BITS;
  26
  27     type ram_type is array (0 to SIZE - 1) of std_logic_vector(WIDTH - 1 downto 0);
  28     signal ram : ram_type;
  29     attribute ram_style : string;
  30     attribute ram_style of ram : signal is "block";
  31     attribute ram_decomp : string;
  32     attribute ram_decomp of ram : signal is "power";
  33
  34 begin
  35     process(clk)
  36     begin
  37         if rising_edge(clk) then
  38             if wr_en = '1' then
  39                 ram(to_integer(unsigned(wr_addr))) <= wr_data;
  40             end if;
  41             if rd_en = '1' then
  42                 rd_data <= ram(to_integer(unsigned(rd_addr)));
  43             end if;
  44         end if;
  45     end process;
  46 end;