common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.utils.all;
   7 use work.decode_types.all;
   8
   9 package common is
  10     -- Processor Version Number
  11     constant PVR_MICROWATT  : std_ulogic_vector(31 downto 0) := x"00630000";
  12
  13     -- MSR bit numbers
  14     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  15     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  16     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  17     constant MSR_FP  : integer := (63 - 50);    -- Floating Point available
  18     constant MSR_FE0 : integer := (63 - 52);    -- Floating Exception mode
  19     constant MSR_SE  : integer := (63 - 53);    -- Single-step bit of TE field
  20     constant MSR_BE  : integer := (63 - 54);    -- Branch trace bit of TE field
  21     constant MSR_FE1 : integer := (63 - 55);    -- Floating Exception mode
  22     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  23     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  24     constant MSR_PMM : integer := (63 - 61);    -- Performance Monitor Mark
  25     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  26     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  27
  28     -- SPR numbers
  29     subtype spr_num_t is integer range 0 to 1023;
  30
  31     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  32
  33     constant SPR_XER    : spr_num_t := 1;
  34     constant SPR_LR     : spr_num_t := 8;
  35     constant SPR_CTR    : spr_num_t := 9;
  36     constant SPR_TAR    : spr_num_t := 815;
  37     constant SPR_DSISR  : spr_num_t := 18;
  38     constant SPR_DAR    : spr_num_t := 19;
  39     constant SPR_TB     : spr_num_t := 268;
  40     constant SPR_TBU    : spr_num_t := 269;
  41     constant SPR_DEC    : spr_num_t := 22;
  42     constant SPR_SRR0   : spr_num_t := 26;
  43     constant SPR_SRR1   : spr_num_t := 27;
  44     constant SPR_CFAR   : spr_num_t := 28;
  45     constant SPR_HSRR0  : spr_num_t := 314;
  46     constant SPR_HSRR1  : spr_num_t := 315;
  47     constant SPR_SPRG0  : spr_num_t := 272;
  48     constant SPR_SPRG1  : spr_num_t := 273;
  49     constant SPR_SPRG2  : spr_num_t := 274;
  50     constant SPR_SPRG3  : spr_num_t := 275;
  51     constant SPR_SPRG3U : spr_num_t := 259;
  52     constant SPR_HSPRG0 : spr_num_t := 304;
  53     constant SPR_HSPRG1 : spr_num_t := 305;
  54     constant SPR_PID    : spr_num_t := 48;
  55     constant SPR_PTCR   : spr_num_t := 464;
  56     constant SPR_PVR    : spr_num_t := 287;
  57
  58     -- PMU registers
  59     constant SPR_UPMC1  : spr_num_t := 771;
  60     constant SPR_UPMC2  : spr_num_t := 772;
  61     constant SPR_UPMC3  : spr_num_t := 773;
  62     constant SPR_UPMC4  : spr_num_t := 774;
  63     constant SPR_UPMC5  : spr_num_t := 775;
  64     constant SPR_UPMC6  : spr_num_t := 776;
  65     constant SPR_UMMCR0 : spr_num_t := 779;
  66     constant SPR_UMMCR1 : spr_num_t := 782;
  67     constant SPR_UMMCR2 : spr_num_t := 769;
  68     constant SPR_UMMCRA : spr_num_t := 770;
  69     constant SPR_USIER  : spr_num_t := 768;
  70     constant SPR_USIAR  : spr_num_t := 780;
  71     constant SPR_USDAR  : spr_num_t := 781;
  72     constant SPR_PMC1   : spr_num_t := 787;
  73     constant SPR_PMC2   : spr_num_t := 788;
  74     constant SPR_PMC3   : spr_num_t := 789;
  75     constant SPR_PMC4   : spr_num_t := 790;
  76     constant SPR_PMC5   : spr_num_t := 791;
  77     constant SPR_PMC6   : spr_num_t := 792;
  78     constant SPR_MMCR0  : spr_num_t := 795;
  79     constant SPR_MMCR1  : spr_num_t := 798;
  80     constant SPR_MMCR2  : spr_num_t := 785;
  81     constant SPR_MMCRA  : spr_num_t := 786;
  82     constant SPR_SIER   : spr_num_t := 784;
  83     constant SPR_SIAR   : spr_num_t := 796;
  84     constant SPR_SDAR   : spr_num_t := 797;
  85
  86     -- GPR indices in the register file (GPR only)
  87     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  88
  89     -- Extended GPR index (can hold an SPR or a FPR)
  90     subtype gspr_index_t is std_ulogic_vector(6 downto 0);
  91
  92     -- FPR indices
  93     subtype fpr_index_t is std_ulogic_vector(4 downto 0);
  94
  95     -- Some SPRs are stored in the register file, they use the magic
  96     -- GPR numbers above 31.
  97     --
  98     -- The function fast_spr_num() returns the corresponding fast
  99     -- pseudo-GPR number for a given SPR number. The result MSB
 100     -- indicates if this is indeed a fast SPR. If clear, then
 101     -- the SPR is not stored in the GPR file.
 102     --
 103     -- FPRs are also stored in the register file, using GSPR
 104     -- numbers from 64 to 95.
 105     --
 106     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
 107
 108     -- Indices conversion functions
 109     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
 110     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
 111     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
 112     function is_fast_spr(s: gspr_index_t) return std_ulogic;
 113     function fpr_to_gspr(f: fpr_index_t) return gspr_index_t;
 114
 115     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
 116     -- in the CR file as a kind of CR extension (with a separate write
 117     -- control). The rest is stored as a fast SPR.
 118     type xer_common_t is record
 119         ca : std_ulogic;
 120         ca32 : std_ulogic;
 121         ov : std_ulogic;
 122         ov32 : std_ulogic;
 123         so : std_ulogic;
 124     end record;
 125     constant xerc_init : xer_common_t := (others => '0');
 126
 127     -- FPSCR bit numbers
 128     constant FPSCR_FX     : integer := 63 - 32;
 129     constant FPSCR_FEX    : integer := 63 - 33;
 130     constant FPSCR_VX     : integer := 63 - 34;
 131     constant FPSCR_OX     : integer := 63 - 35;
 132     constant FPSCR_UX     : integer := 63 - 36;
 133     constant FPSCR_ZX     : integer := 63 - 37;
 134     constant FPSCR_XX     : integer := 63 - 38;
 135     constant FPSCR_VXSNAN : integer := 63 - 39;
 136     constant FPSCR_VXISI  : integer := 63 - 40;
 137     constant FPSCR_VXIDI  : integer := 63 - 41;
 138     constant FPSCR_VXZDZ  : integer := 63 - 42;
 139     constant FPSCR_VXIMZ  : integer := 63 - 43;
 140     constant FPSCR_VXVC   : integer := 63 - 44;
 141     constant FPSCR_FR     : integer := 63 - 45;
 142     constant FPSCR_FI     : integer := 63 - 46;
 143     constant FPSCR_C      : integer := 63 - 47;
 144     constant FPSCR_FL     : integer := 63 - 48;
 145     constant FPSCR_FG     : integer := 63 - 49;
 146     constant FPSCR_FE     : integer := 63 - 50;
 147     constant FPSCR_FU     : integer := 63 - 51;
 148     constant FPSCR_VXSOFT : integer := 63 - 53;
 149     constant FPSCR_VXSQRT : integer := 63 - 54;
 150     constant FPSCR_VXCVI  : integer := 63 - 55;
 151     constant FPSCR_VE     : integer := 63 - 56;
 152     constant FPSCR_OE     : integer := 63 - 57;
 153     constant FPSCR_UE     : integer := 63 - 58;
 154     constant FPSCR_ZE     : integer := 63 - 59;
 155     constant FPSCR_XE     : integer := 63 - 60;
 156     constant FPSCR_NI     : integer := 63 - 61;
 157     constant FPSCR_RN     : integer := 63 - 63;
 158
 159     -- Real addresses
 160     -- REAL_ADDR_BITS is the number of real address bits that we store
 161     constant REAL_ADDR_BITS : positive := 56;
 162     subtype real_addr_t is std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
 163     function addr_to_real(addr: std_ulogic_vector(63 downto 0)) return real_addr_t;
 164
 165     -- Used for tracking instruction completion and pending register writes
 166     constant TAG_COUNT : positive := 4;
 167     constant TAG_NUMBER_BITS : natural := log2(TAG_COUNT);
 168     subtype tag_number_t is integer range 0 to TAG_COUNT - 1;
 169     subtype tag_index_t is unsigned(TAG_NUMBER_BITS - 1 downto 0);
 170     type instr_tag_t is record
 171         tag   : tag_number_t;
 172         valid : std_ulogic;
 173     end record;
 174     constant instr_tag_init : instr_tag_t := (tag => 0, valid => '0');
 175     function tag_match(tag1 : instr_tag_t; tag2 : instr_tag_t) return boolean;
 176
 177     subtype intr_vector_t is integer range 0 to 16#fff#;
 178
 179     -- For now, fixed 16 sources, make this either a parametric
 180     -- package of some sort or an unconstrainted array.
 181     type ics_to_icp_t is record
 182         -- Level interrupts only, ICS just keeps prsenting the
 183         -- highest priority interrupt. Once handling edge, something
 184         -- smarter involving handshake & reject support will be needed
 185         src : std_ulogic_vector(3 downto 0);
 186         pri : std_ulogic_vector(7 downto 0);
 187     end record;
 188
 189     -- This needs to die...
 190     type ctrl_t is record
 191         tb: std_ulogic_vector(63 downto 0);
 192         dec: std_ulogic_vector(63 downto 0);
 193         msr: std_ulogic_vector(63 downto 0);
 194         cfar: std_ulogic_vector(63 downto 0);
 195     end record;
 196
 197     type Fetch1ToIcacheType is record
 198         req: std_ulogic;
 199         virt_mode : std_ulogic;
 200         priv_mode : std_ulogic;
 201         big_endian : std_ulogic;
 202         stop_mark: std_ulogic;
 203         predicted : std_ulogic;
 204         pred_ntaken : std_ulogic;
 205         nia: std_ulogic_vector(63 downto 0);
 206     end record;
 207
 208     type IcacheToDecode1Type is record
 209         valid: std_ulogic;
 210         stop_mark: std_ulogic;
 211         fetch_failed: std_ulogic;
 212         nia: std_ulogic_vector(63 downto 0);
 213         insn: std_ulogic_vector(31 downto 0);
 214         big_endian: std_ulogic;
 215         next_predicted: std_ulogic;
 216         next_pred_ntaken: std_ulogic;
 217     end record;
 218
 219     type IcacheEventType is record
 220         icache_miss : std_ulogic;
 221         itlb_miss_resolved : std_ulogic;
 222     end record;
 223
 224     type Decode1ToDecode2Type is record
 225         valid: std_ulogic;
 226         stop_mark : std_ulogic;
 227         nia: std_ulogic_vector(63 downto 0);
 228         insn: std_ulogic_vector(31 downto 0);
 229         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
 230         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
 231         ispro: gspr_index_t; -- (G)SPR written with LR or CTR
 232         decode: decode_rom_t;
 233         br_pred: std_ulogic; -- Branch was predicted to be taken
 234         big_endian: std_ulogic;
 235     end record;
 236     constant Decode1ToDecode2Init : Decode1ToDecode2Type :=
 237         (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'),
 238          ispr1 => (others => '0'), ispr2 => (others => '0'), ispro => (others => '0'),
 239          decode => decode_rom_init, br_pred => '0', big_endian => '0');
 240
 241     type Decode1ToFetch1Type is record
 242         redirect     : std_ulogic;
 243         redirect_nia : std_ulogic_vector(63 downto 0);
 244     end record;
 245
 246     type bypass_data_t is record
 247         tag  : instr_tag_t;
 248         data : std_ulogic_vector(63 downto 0);
 249     end record;
 250     constant bypass_data_init : bypass_data_t := (tag => instr_tag_init, data => (others => '0'));
 251
 252     type cr_bypass_data_t is record
 253         tag  : instr_tag_t;
 254         data : std_ulogic_vector(31 downto 0);
 255     end record;
 256     constant cr_bypass_data_init : cr_bypass_data_t := (tag => instr_tag_init, data => (others => '0'));
 257
 258     type Decode2ToExecute1Type is record
 259         valid: std_ulogic;
 260         unit : unit_t;
 261         fac : facility_t;
 262         insn_type: insn_type_t;
 263         nia: std_ulogic_vector(63 downto 0);
 264         instr_tag : instr_tag_t;
 265         write_reg: gspr_index_t;
 266         write_reg_enable: std_ulogic;
 267         read_reg1: gspr_index_t;
 268         read_reg2: gspr_index_t;
 269         read_data1: std_ulogic_vector(63 downto 0);
 270         read_data2: std_ulogic_vector(63 downto 0);
 271         read_data3: std_ulogic_vector(63 downto 0);
 272         cr: std_ulogic_vector(31 downto 0);
 273         xerc: xer_common_t;
 274         lr: std_ulogic;
 275         br_abs: std_ulogic;
 276         rc: std_ulogic;
 277         oe: std_ulogic;
 278         invert_a: std_ulogic;
 279         addm1 : std_ulogic;
 280         invert_out: std_ulogic;
 281         input_carry: carry_in_t;
 282         output_carry: std_ulogic;
 283         input_cr: std_ulogic;
 284         output_cr: std_ulogic;
 285         output_xer: std_ulogic;
 286         is_32bit: std_ulogic;
 287         is_signed: std_ulogic;
 288         insn: std_ulogic_vector(31 downto 0);
 289         data_len: std_ulogic_vector(3 downto 0);
 290         byte_reverse : std_ulogic;
 291         sign_extend : std_ulogic;                       -- do we need to sign extend?
 292         update : std_ulogic;                            -- is this an update instruction?
 293         reserve : std_ulogic;                           -- set for larx/stcx
 294         br_pred : std_ulogic;
 295         result_sel : std_ulogic_vector(2 downto 0);     -- select source of result
 296         sub_select : std_ulogic_vector(2 downto 0);     -- sub-result selection
 297         repeat : std_ulogic;                            -- set if instruction is cracked into two ops
 298         second : std_ulogic;                            -- set if this is the second op
 299     end record;
 300     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 301         (valid => '0', unit => NONE, fac => NONE, insn_type => OP_ILLEGAL, instr_tag => instr_tag_init,
 302          write_reg_enable => '0',
 303          lr => '0', br_abs => '0', rc => '0', oe => '0', invert_a => '0', addm1 => '0',
 304          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0',
 305          output_cr => '0', output_xer => '0',
 306          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0', br_pred => '0',
 307          byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'),
 308          read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'),
 309          cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'),
 310          result_sel => "000", sub_select => "000",
 311          repeat => '0', second => '0', others => (others => '0'));
 312
 313     type MultiplyInputType is record
 314         valid: std_ulogic;
 315         data1: std_ulogic_vector(63 downto 0);
 316         data2: std_ulogic_vector(63 downto 0);
 317         addend: std_ulogic_vector(127 downto 0);
 318         is_32bit: std_ulogic;
 319         not_result: std_ulogic;
 320     end record;
 321     constant MultiplyInputInit : MultiplyInputType := (valid => '0',
 322                                                        is_32bit => '0', not_result => '0',
 323                                                        others => (others => '0'));
 324
 325     type MultiplyOutputType is record
 326         valid: std_ulogic;
 327         result: std_ulogic_vector(127 downto 0);
 328         overflow : std_ulogic;
 329     end record;
 330     constant MultiplyOutputInit : MultiplyOutputType := (valid => '0', overflow => '0',
 331                                                          others => (others => '0'));
 332
 333     type Execute1ToDividerType is record
 334         valid: std_ulogic;
 335         dividend: std_ulogic_vector(63 downto 0);
 336         divisor: std_ulogic_vector(63 downto 0);
 337         is_signed: std_ulogic;
 338         is_32bit: std_ulogic;
 339         is_extended: std_ulogic;
 340         is_modulus: std_ulogic;
 341         neg_result: std_ulogic;
 342     end record;
 343     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 344                                                               is_extended => '0', is_modulus => '0',
 345                                                               neg_result => '0', others => (others => '0'));
 346
 347     type PMUEventType is record
 348         no_instr_avail      : std_ulogic;
 349         dispatch            : std_ulogic;
 350         ext_interrupt       : std_ulogic;
 351         instr_complete      : std_ulogic;
 352         fp_complete         : std_ulogic;
 353         ld_complete         : std_ulogic;
 354         st_complete         : std_ulogic;
 355         br_taken_complete   : std_ulogic;
 356         br_mispredict       : std_ulogic;
 357         ipref_discard       : std_ulogic;
 358         itlb_miss           : std_ulogic;
 359         itlb_miss_resolved  : std_ulogic;
 360         icache_miss         : std_ulogic;
 361         dc_miss_resolved    : std_ulogic;
 362         dc_load_miss        : std_ulogic;
 363         dc_ld_miss_resolved : std_ulogic;
 364         dc_store_miss       : std_ulogic;
 365         dtlb_miss           : std_ulogic;
 366         dtlb_miss_resolved  : std_ulogic;
 367         ld_miss_nocache     : std_ulogic;
 368         ld_fill_nocache     : std_ulogic;
 369     end record;
 370     constant PMUEventInit : PMUEventType := (others => '0');
 371
 372     type Execute1ToPMUType is record
 373         mfspr   : std_ulogic;
 374         mtspr   : std_ulogic;
 375         spr_num : std_ulogic_vector(4 downto 0);
 376         spr_val : std_ulogic_vector(63 downto 0);
 377         tbbits  : std_ulogic_vector(3 downto 0);        -- event bits from timebase
 378         pmm_msr : std_ulogic;                           -- PMM bit from MSR
 379         pr_msr  : std_ulogic;                           -- PR bit from MSR
 380         run     : std_ulogic;
 381         nia     : std_ulogic_vector(63 downto 0);
 382         addr    : std_ulogic_vector(63 downto 0);
 383         addr_v  : std_ulogic;
 384         occur   : PMUEventType;
 385     end record;
 386
 387     type PMUToExecute1Type is record
 388         spr_val : std_ulogic_vector(63 downto 0);
 389         intr    : std_ulogic;
 390     end record;
 391
 392     type Decode2ToRegisterFileType is record
 393         read1_enable : std_ulogic;
 394         read1_reg : gspr_index_t;
 395         read2_enable : std_ulogic;
 396         read2_reg : gspr_index_t;
 397         read3_enable : std_ulogic;
 398         read3_reg : gspr_index_t;
 399     end record;
 400
 401     type RegisterFileToDecode2Type is record
 402         read1_data : std_ulogic_vector(63 downto 0);
 403         read2_data : std_ulogic_vector(63 downto 0);
 404         read3_data : std_ulogic_vector(63 downto 0);
 405     end record;
 406
 407     type Decode2ToCrFileType is record
 408         read : std_ulogic;
 409     end record;
 410
 411     type CrFileToDecode2Type is record
 412         read_cr_data   : std_ulogic_vector(31 downto 0);
 413         read_xerc_data : xer_common_t;
 414     end record;
 415
 416     type Execute1ToLoadstore1Type is record
 417         valid : std_ulogic;
 418         op : insn_type_t;                               -- what ld/st or m[tf]spr or TLB op to do
 419         nia : std_ulogic_vector(63 downto 0);
 420         insn : std_ulogic_vector(31 downto 0);
 421         instr_tag : instr_tag_t;
 422         addr1 : std_ulogic_vector(63 downto 0);
 423         addr2 : std_ulogic_vector(63 downto 0);
 424         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 425         write_reg : gspr_index_t;
 426         length : std_ulogic_vector(3 downto 0);
 427         ci : std_ulogic;                                -- cache-inhibited load/store
 428         byte_reverse : std_ulogic;
 429         sign_extend : std_ulogic;                       -- do we need to sign extend?
 430         update : std_ulogic;                            -- is this an update instruction?
 431         xerc : xer_common_t;
 432         reserve : std_ulogic;                           -- set for larx/stcx.
 433         rc : std_ulogic;                                -- set for stcx.
 434         virt_mode : std_ulogic;                         -- do translation through TLB
 435         priv_mode : std_ulogic;                         -- privileged mode (MSR[PR] = 0)
 436         mode_32bit : std_ulogic;                        -- trim addresses to 32 bits
 437         is_32bit : std_ulogic;
 438         repeat : std_ulogic;
 439         second : std_ulogic;
 440         msr : std_ulogic_vector(63 downto 0);
 441     end record;
 442     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type :=
 443         (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
 444          sign_extend => '0', update => '0', xerc => xerc_init,
 445          reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
 446          nia => (others => '0'), insn => (others => '0'),
 447          instr_tag => instr_tag_init,
 448          addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'),
 449          write_reg => (others => '0'),
 450          length => (others => '0'),
 451          mode_32bit => '0', is_32bit => '0',
 452          repeat => '0', second => '0',
 453          msr => (others => '0'));
 454
 455     type Loadstore1ToExecute1Type is record
 456         busy : std_ulogic;
 457         in_progress : std_ulogic;
 458         interrupt : std_ulogic;
 459     end record;
 460
 461     type Loadstore1ToDcacheType is record
 462         valid : std_ulogic;
 463         hold : std_ulogic;
 464         load : std_ulogic;                              -- is this a load
 465         dcbz : std_ulogic;
 466         nc : std_ulogic;
 467         reserve : std_ulogic;
 468         atomic : std_ulogic;                            -- part of a multi-transfer atomic op
 469         atomic_last : std_ulogic;
 470         virt_mode : std_ulogic;
 471         priv_mode : std_ulogic;
 472         addr : std_ulogic_vector(63 downto 0);
 473         data : std_ulogic_vector(63 downto 0);          -- valid the cycle after .valid = 1
 474         byte_sel : std_ulogic_vector(7 downto 0);
 475     end record;
 476
 477     type DcacheToLoadstore1Type is record
 478         valid : std_ulogic;
 479         data : std_ulogic_vector(63 downto 0);
 480         store_done : std_ulogic;
 481         error : std_ulogic;
 482         cache_paradox : std_ulogic;
 483     end record;
 484
 485     type DcacheEventType is record
 486         load_miss          : std_ulogic;
 487         store_miss         : std_ulogic;
 488         dcache_refill      : std_ulogic;
 489         dtlb_miss          : std_ulogic;
 490         dtlb_miss_resolved : std_ulogic;
 491     end record;
 492
 493     type Loadstore1ToMmuType is record
 494         valid : std_ulogic;
 495         tlbie : std_ulogic;
 496         slbia : std_ulogic;
 497         mtspr : std_ulogic;
 498         iside : std_ulogic;
 499         load  : std_ulogic;
 500         priv  : std_ulogic;
 501         sprn  : std_ulogic_vector(9 downto 0);
 502         addr  : std_ulogic_vector(63 downto 0);
 503         rs    : std_ulogic_vector(63 downto 0);
 504     end record;
 505
 506     type MmuToLoadstore1Type is record
 507         done       : std_ulogic;
 508         err        : std_ulogic;
 509         invalid    : std_ulogic;
 510         badtree    : std_ulogic;
 511         segerr     : std_ulogic;
 512         perm_error : std_ulogic;
 513         rc_error   : std_ulogic;
 514         sprval     : std_ulogic_vector(63 downto 0);
 515     end record;
 516
 517     type MmuToDcacheType is record
 518         valid : std_ulogic;
 519         tlbie : std_ulogic;
 520         doall : std_ulogic;
 521         tlbld : std_ulogic;
 522         addr  : std_ulogic_vector(63 downto 0);
 523         pte   : std_ulogic_vector(63 downto 0);
 524     end record;
 525
 526     type DcacheToMmuType is record
 527         stall : std_ulogic;
 528         done  : std_ulogic;
 529         err   : std_ulogic;
 530         data  : std_ulogic_vector(63 downto 0);
 531     end record;
 532
 533     type MmuToIcacheType is record
 534         tlbld : std_ulogic;
 535         tlbie : std_ulogic;
 536         doall : std_ulogic;
 537         addr  : std_ulogic_vector(63 downto 0);
 538         pte   : std_ulogic_vector(63 downto 0);
 539     end record;
 540
 541     type Loadstore1ToWritebackType is record
 542         valid : std_ulogic;
 543         instr_tag : instr_tag_t;
 544         write_enable: std_ulogic;
 545         write_reg : gspr_index_t;
 546         write_data : std_ulogic_vector(63 downto 0);
 547         xerc : xer_common_t;
 548         rc : std_ulogic;
 549         store_done : std_ulogic;
 550         interrupt : std_ulogic;
 551         intr_vec : intr_vector_t;
 552         srr0: std_ulogic_vector(63 downto 0);
 553         srr1: std_ulogic_vector(15 downto 0);
 554     end record;
 555     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType :=
 556         (valid => '0', instr_tag => instr_tag_init, write_enable => '0',
 557          write_reg => (others => '0'), write_data => (others => '0'),
 558          xerc => xerc_init, rc => '0', store_done => '0',
 559          interrupt => '0', intr_vec => 0,
 560          srr0 => (others => '0'), srr1 => (others => '0'));
 561
 562     type Loadstore1EventType is record
 563         load_complete  : std_ulogic;
 564         store_complete : std_ulogic;
 565         itlb_miss      : std_ulogic;
 566     end record;
 567
 568     type Execute1ToWritebackType is record
 569         valid: std_ulogic;
 570         instr_tag : instr_tag_t;
 571         rc : std_ulogic;
 572         mode_32bit : std_ulogic;
 573         write_enable : std_ulogic;
 574         write_reg: gspr_index_t;
 575         write_data: std_ulogic_vector(63 downto 0);
 576         write_cr_enable : std_ulogic;
 577         write_cr_mask : std_ulogic_vector(7 downto 0);
 578         write_cr_data : std_ulogic_vector(31 downto 0);
 579         write_xerc_enable : std_ulogic;
 580         xerc : xer_common_t;
 581         interrupt : std_ulogic;
 582         intr_vec : intr_vector_t;
 583         redirect: std_ulogic;
 584         redir_mode: std_ulogic_vector(3 downto 0);
 585         last_nia: std_ulogic_vector(63 downto 0);
 586         br_offset: std_ulogic_vector(63 downto 0);
 587         br_last: std_ulogic;
 588         br_taken: std_ulogic;
 589         abs_br: std_ulogic;
 590         srr1: std_ulogic_vector(15 downto 0);
 591         msr: std_ulogic_vector(63 downto 0);
 592     end record;
 593     constant Execute1ToWritebackInit : Execute1ToWritebackType :=
 594         (valid => '0', instr_tag => instr_tag_init, rc => '0', mode_32bit => '0',
 595          write_enable => '0', write_cr_enable => '0',
 596          write_xerc_enable => '0', xerc => xerc_init,
 597          write_data => (others => '0'), write_cr_mask => (others => '0'),
 598          write_cr_data => (others => '0'), write_reg => (others => '0'),
 599          interrupt => '0', intr_vec => 0, redirect => '0', redir_mode => "0000",
 600          last_nia => (others => '0'), br_offset => (others => '0'),
 601          br_last => '0', br_taken => '0', abs_br => '0',
 602          srr1 => (others => '0'), msr => (others => '0'));
 603
 604     type Execute1ToFPUType is record
 605         valid   : std_ulogic;
 606         op      : insn_type_t;
 607         nia     : std_ulogic_vector(63 downto 0);
 608         itag    : instr_tag_t;
 609         insn    : std_ulogic_vector(31 downto 0);
 610         single  : std_ulogic;
 611         fe_mode : std_ulogic_vector(1 downto 0);
 612         fra     : std_ulogic_vector(63 downto 0);
 613         frb     : std_ulogic_vector(63 downto 0);
 614         frc     : std_ulogic_vector(63 downto 0);
 615         frt     : gspr_index_t;
 616         rc      : std_ulogic;
 617         out_cr  : std_ulogic;
 618     end record;
 619     constant Execute1ToFPUInit : Execute1ToFPUType := (valid => '0', op => OP_ILLEGAL, nia => (others => '0'),
 620                                                        itag => instr_tag_init,
 621                                                        insn  => (others => '0'), fe_mode => "00", rc => '0',
 622                                                        fra => (others => '0'), frb => (others => '0'),
 623                                                        frc => (others => '0'), frt => (others => '0'),
 624                                                        single => '0', out_cr => '0');
 625
 626     type FPUToExecute1Type is record
 627         busy      : std_ulogic;
 628         exception : std_ulogic;
 629     end record;
 630     constant FPUToExecute1Init : FPUToExecute1Type := (others => '0');
 631
 632     type FPUToWritebackType is record
 633         valid           : std_ulogic;
 634         interrupt       : std_ulogic;
 635         instr_tag       : instr_tag_t;
 636         write_enable    : std_ulogic;
 637         write_reg       : gspr_index_t;
 638         write_data      : std_ulogic_vector(63 downto 0);
 639         write_cr_enable : std_ulogic;
 640         write_cr_mask   : std_ulogic_vector(7 downto 0);
 641         write_cr_data   : std_ulogic_vector(31 downto 0);
 642         intr_vec        : intr_vector_t;
 643         srr0            : std_ulogic_vector(63 downto 0);
 644         srr1            : std_ulogic_vector(15 downto 0);
 645     end record;
 646     constant FPUToWritebackInit : FPUToWritebackType :=
 647         (valid => '0', interrupt => '0', instr_tag => instr_tag_init,
 648          write_enable => '0', write_reg => (others => '0'),
 649          write_cr_enable => '0', write_cr_mask => (others => '0'),
 650          write_cr_data => (others => '0'),
 651          intr_vec => 0, srr1 => (others => '0'),
 652          others => (others => '0'));
 653
 654     type DividerToExecute1Type is record
 655         valid: std_ulogic;
 656         write_reg_data: std_ulogic_vector(63 downto 0);
 657         overflow : std_ulogic;
 658     end record;
 659     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 660                                                                others => (others => '0'));
 661
 662     type WritebackToFetch1Type is record
 663         redirect: std_ulogic;
 664         virt_mode: std_ulogic;
 665         priv_mode: std_ulogic;
 666         big_endian: std_ulogic;
 667         mode_32bit: std_ulogic;
 668         redirect_nia: std_ulogic_vector(63 downto 0);
 669         br_nia : std_ulogic_vector(63 downto 0);
 670         br_last : std_ulogic;
 671         br_taken : std_ulogic;
 672     end record;
 673     constant WritebackToFetch1Init : WritebackToFetch1Type :=
 674         (redirect => '0', virt_mode => '0', priv_mode => '0', big_endian => '0',
 675          mode_32bit => '0', redirect_nia => (others => '0'),
 676          br_last => '0', br_taken => '0', br_nia => (others => '0'));
 677
 678     type WritebackToRegisterFileType is record
 679         write_reg : gspr_index_t;
 680         write_data : std_ulogic_vector(63 downto 0);
 681         write_enable : std_ulogic;
 682     end record;
 683     constant WritebackToRegisterFileInit : WritebackToRegisterFileType :=
 684         (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
 685
 686     type WritebackToCrFileType is record
 687         write_cr_enable : std_ulogic;
 688         write_cr_mask : std_ulogic_vector(7 downto 0);
 689         write_cr_data : std_ulogic_vector(31 downto 0);
 690         write_xerc_enable : std_ulogic;
 691         write_xerc_data : xer_common_t;
 692     end record;
 693     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 694                                                                write_xerc_data => xerc_init,
 695                                                                write_cr_mask => (others => '0'),
 696                                                                write_cr_data => (others => '0'));
 697
 698     type WritebackEventType is record
 699         instr_complete : std_ulogic;
 700         fp_complete    : std_ulogic;
 701     end record;
 702
 703 end common;
 704
 705 package body common is
 706     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 707     begin
 708         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 709     end;
 710     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 711        variable n : integer range 0 to 31;
 712        -- tmp variable introduced as workaround for VCS compilation
 713        -- simulation was failing with subtype constraint mismatch error
 714        -- see GitHub PR #173
 715        variable tmp : std_ulogic_vector(4 downto 0);
 716     begin
 717        case spr is
 718        when SPR_LR =>
 719            n := 0;              -- N.B. decode2 relies on this specific value
 720        when SPR_CTR =>
 721            n := 1;              -- N.B. decode2 relies on this specific value
 722        when SPR_SRR0 =>
 723            n := 2;
 724        when SPR_SRR1 =>
 725            n := 3;
 726        when SPR_HSRR0 =>
 727            n := 4;
 728        when SPR_HSRR1 =>
 729            n := 5;
 730        when SPR_SPRG0 =>
 731            n := 6;
 732        when SPR_SPRG1 =>
 733            n := 7;
 734        when SPR_SPRG2 =>
 735            n := 8;
 736        when SPR_SPRG3 | SPR_SPRG3U =>
 737            n := 9;
 738        when SPR_HSPRG0 =>
 739            n := 10;
 740        when SPR_HSPRG1 =>
 741            n := 11;
 742        when SPR_XER =>
 743            n := 12;
 744        when SPR_TAR =>
 745            n := 13;
 746        when others =>
 747            n := 0;
 748            return "0000000";
 749        end case;
 750        tmp := std_ulogic_vector(to_unsigned(n, 5));
 751        return "01" & tmp;
 752     end;
 753
 754     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 755     begin
 756         return i(4 downto 0);
 757     end;
 758
 759     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 760     begin
 761         return "00" & i;
 762     end;
 763
 764     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 765     begin
 766         if s(5) = '1' then
 767             return s;
 768         else
 769             return gpr_to_gspr(g);
 770         end if;
 771     end;
 772
 773     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 774     begin
 775         return s(5);
 776     end;
 777
 778     function fpr_to_gspr(f: fpr_index_t) return gspr_index_t is
 779     begin
 780         return "10" & f;
 781     end;
 782
 783     function tag_match(tag1 : instr_tag_t; tag2 : instr_tag_t) return boolean is
 784     begin
 785         return tag1.valid = '1' and tag2.valid = '1' and tag1.tag = tag2.tag;
 786     end;
 787
 788     function addr_to_real(addr: std_ulogic_vector(63 downto 0)) return real_addr_t is
 789     begin
 790         return addr(real_addr_t'range);
 791     end;
 792 end common;