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[microwatt.git] / common.vhdl
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4
5 library work;
6 use work.utils.all;
7 use work.decode_types.all;
8
9 package common is
10 -- Processor Version Number
11 constant PVR_MICROWATT : std_ulogic_vector(31 downto 0) := x"00630000";
12
13 -- MSR bit numbers
14 constant MSR_SF : integer := (63 - 0); -- Sixty-Four bit mode
15 constant MSR_EE : integer := (63 - 48); -- External interrupt Enable
16 constant MSR_PR : integer := (63 - 49); -- PRoblem state
17 constant MSR_FP : integer := (63 - 50); -- Floating Point available
18 constant MSR_FE0 : integer := (63 - 52); -- Floating Exception mode
19 constant MSR_SE : integer := (63 - 53); -- Single-step bit of TE field
20 constant MSR_BE : integer := (63 - 54); -- Branch trace bit of TE field
21 constant MSR_FE1 : integer := (63 - 55); -- Floating Exception mode
22 constant MSR_IR : integer := (63 - 58); -- Instruction Relocation
23 constant MSR_DR : integer := (63 - 59); -- Data Relocation
24 constant MSR_PMM : integer := (63 - 61); -- Performance Monitor Mark
25 constant MSR_RI : integer := (63 - 62); -- Recoverable Interrupt
26 constant MSR_LE : integer := (63 - 63); -- Little Endian
27
28 -- SPR numbers
29 subtype spr_num_t is integer range 0 to 1023;
30
31 function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
32
33 constant SPR_XER : spr_num_t := 1;
34 constant SPR_LR : spr_num_t := 8;
35 constant SPR_CTR : spr_num_t := 9;
36 constant SPR_TAR : spr_num_t := 815;
37 constant SPR_DSISR : spr_num_t := 18;
38 constant SPR_DAR : spr_num_t := 19;
39 constant SPR_TB : spr_num_t := 268;
40 constant SPR_TBU : spr_num_t := 269;
41 constant SPR_DEC : spr_num_t := 22;
42 constant SPR_SRR0 : spr_num_t := 26;
43 constant SPR_SRR1 : spr_num_t := 27;
44 constant SPR_CFAR : spr_num_t := 28;
45 constant SPR_HSRR0 : spr_num_t := 314;
46 constant SPR_HSRR1 : spr_num_t := 315;
47 constant SPR_SPRG0 : spr_num_t := 272;
48 constant SPR_SPRG1 : spr_num_t := 273;
49 constant SPR_SPRG2 : spr_num_t := 274;
50 constant SPR_SPRG3 : spr_num_t := 275;
51 constant SPR_SPRG3U : spr_num_t := 259;
52 constant SPR_HSPRG0 : spr_num_t := 304;
53 constant SPR_HSPRG1 : spr_num_t := 305;
54 constant SPR_PID : spr_num_t := 48;
55 constant SPR_PTCR : spr_num_t := 464;
56 constant SPR_PVR : spr_num_t := 287;
57
58 -- PMU registers
59 constant SPR_UPMC1 : spr_num_t := 771;
60 constant SPR_UPMC2 : spr_num_t := 772;
61 constant SPR_UPMC3 : spr_num_t := 773;
62 constant SPR_UPMC4 : spr_num_t := 774;
63 constant SPR_UPMC5 : spr_num_t := 775;
64 constant SPR_UPMC6 : spr_num_t := 776;
65 constant SPR_UMMCR0 : spr_num_t := 779;
66 constant SPR_UMMCR1 : spr_num_t := 782;
67 constant SPR_UMMCR2 : spr_num_t := 769;
68 constant SPR_UMMCRA : spr_num_t := 770;
69 constant SPR_USIER : spr_num_t := 768;
70 constant SPR_USIAR : spr_num_t := 780;
71 constant SPR_USDAR : spr_num_t := 781;
72 constant SPR_PMC1 : spr_num_t := 787;
73 constant SPR_PMC2 : spr_num_t := 788;
74 constant SPR_PMC3 : spr_num_t := 789;
75 constant SPR_PMC4 : spr_num_t := 790;
76 constant SPR_PMC5 : spr_num_t := 791;
77 constant SPR_PMC6 : spr_num_t := 792;
78 constant SPR_MMCR0 : spr_num_t := 795;
79 constant SPR_MMCR1 : spr_num_t := 798;
80 constant SPR_MMCR2 : spr_num_t := 785;
81 constant SPR_MMCRA : spr_num_t := 786;
82 constant SPR_SIER : spr_num_t := 784;
83 constant SPR_SIAR : spr_num_t := 796;
84 constant SPR_SDAR : spr_num_t := 797;
85
86 -- GPR indices in the register file (GPR only)
87 subtype gpr_index_t is std_ulogic_vector(4 downto 0);
88
89 -- Extended GPR index (can hold a GPR or a FPR)
90 subtype gspr_index_t is std_ulogic_vector(5 downto 0);
91
92 -- FPR indices
93 subtype fpr_index_t is std_ulogic_vector(4 downto 0);
94
95 -- FPRs are stored in the register file, using GSPR
96 -- numbers from 32 to 63.
97 --
98
99 -- Indices conversion functions
100 function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
101 function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
102 function fpr_to_gspr(f: fpr_index_t) return gspr_index_t;
103
104 -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
105 -- in the CR file as a kind of CR extension (with a separate write
106 -- control). The rest is stored in ctrl_t (effectively in execute1).
107 type xer_common_t is record
108 ca : std_ulogic;
109 ca32 : std_ulogic;
110 ov : std_ulogic;
111 ov32 : std_ulogic;
112 so : std_ulogic;
113 end record;
114 constant xerc_init : xer_common_t := (others => '0');
115
116 -- Some SPRs are stored in a pair of small RAMs in execute1
117 -- Even half:
118 subtype ramspr_index_range is natural range 0 to 7;
119 subtype ramspr_index is unsigned(2 downto 0);
120 constant RAMSPR_SRR0 : ramspr_index := to_unsigned(0,3);
121 constant RAMSPR_HSRR0 : ramspr_index := to_unsigned(1,3);
122 constant RAMSPR_SPRG0 : ramspr_index := to_unsigned(2,3);
123 constant RAMSPR_SPRG2 : ramspr_index := to_unsigned(3,3);
124 constant RAMSPR_HSPRG0 : ramspr_index := to_unsigned(4,3);
125 constant RAMSPR_LR : ramspr_index := to_unsigned(5,3); -- must equal RAMSPR_CTR
126 constant RAMSPR_TAR : ramspr_index := to_unsigned(6,3);
127 -- Odd half:
128 constant RAMSPR_SRR1 : ramspr_index := to_unsigned(0,3);
129 constant RAMSPR_HSRR1 : ramspr_index := to_unsigned(1,3);
130 constant RAMSPR_SPRG1 : ramspr_index := to_unsigned(2,3);
131 constant RAMSPR_SPRG3 : ramspr_index := to_unsigned(3,3);
132 constant RAMSPR_HSPRG1 : ramspr_index := to_unsigned(4,3);
133 constant RAMSPR_CTR : ramspr_index := to_unsigned(5,3); -- must equal RAMSPR_LR
134
135 type ram_spr_info is record
136 index : ramspr_index;
137 isodd : std_ulogic;
138 valid : std_ulogic;
139 end record;
140 constant ram_spr_info_init: ram_spr_info := (index => to_unsigned(0,3), others => '0');
141
142 subtype spr_selector is std_ulogic_vector(2 downto 0);
143 type spr_id is record
144 sel : spr_selector;
145 valid : std_ulogic;
146 ispmu : std_ulogic;
147 end record;
148 constant spr_id_init : spr_id := (sel => "000", others => '0');
149
150 constant SPRSEL_TB : spr_selector := 3x"0";
151 constant SPRSEL_TBU : spr_selector := 3x"1";
152 constant SPRSEL_DEC : spr_selector := 3x"2";
153 constant SPRSEL_PVR : spr_selector := 3x"3";
154 constant SPRSEL_LOGA : spr_selector := 3x"4";
155 constant SPRSEL_LOGD : spr_selector := 3x"5";
156 constant SPRSEL_CFAR : spr_selector := 3x"6";
157 constant SPRSEL_XER : spr_selector := 3x"7";
158
159 -- FPSCR bit numbers
160 constant FPSCR_FX : integer := 63 - 32;
161 constant FPSCR_FEX : integer := 63 - 33;
162 constant FPSCR_VX : integer := 63 - 34;
163 constant FPSCR_OX : integer := 63 - 35;
164 constant FPSCR_UX : integer := 63 - 36;
165 constant FPSCR_ZX : integer := 63 - 37;
166 constant FPSCR_XX : integer := 63 - 38;
167 constant FPSCR_VXSNAN : integer := 63 - 39;
168 constant FPSCR_VXISI : integer := 63 - 40;
169 constant FPSCR_VXIDI : integer := 63 - 41;
170 constant FPSCR_VXZDZ : integer := 63 - 42;
171 constant FPSCR_VXIMZ : integer := 63 - 43;
172 constant FPSCR_VXVC : integer := 63 - 44;
173 constant FPSCR_FR : integer := 63 - 45;
174 constant FPSCR_FI : integer := 63 - 46;
175 constant FPSCR_C : integer := 63 - 47;
176 constant FPSCR_FL : integer := 63 - 48;
177 constant FPSCR_FG : integer := 63 - 49;
178 constant FPSCR_FE : integer := 63 - 50;
179 constant FPSCR_FU : integer := 63 - 51;
180 constant FPSCR_VXSOFT : integer := 63 - 53;
181 constant FPSCR_VXSQRT : integer := 63 - 54;
182 constant FPSCR_VXCVI : integer := 63 - 55;
183 constant FPSCR_VE : integer := 63 - 56;
184 constant FPSCR_OE : integer := 63 - 57;
185 constant FPSCR_UE : integer := 63 - 58;
186 constant FPSCR_ZE : integer := 63 - 59;
187 constant FPSCR_XE : integer := 63 - 60;
188 constant FPSCR_NI : integer := 63 - 61;
189 constant FPSCR_RN : integer := 63 - 63;
190
191 -- Real addresses
192 -- REAL_ADDR_BITS is the number of real address bits that we store
193 constant REAL_ADDR_BITS : positive := 56;
194 subtype real_addr_t is std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
195 function addr_to_real(addr: std_ulogic_vector(63 downto 0)) return real_addr_t;
196
197 -- Used for tracking instruction completion and pending register writes
198 constant TAG_COUNT : positive := 4;
199 constant TAG_NUMBER_BITS : natural := log2(TAG_COUNT);
200 subtype tag_number_t is integer range 0 to TAG_COUNT - 1;
201 subtype tag_index_t is unsigned(TAG_NUMBER_BITS - 1 downto 0);
202 type instr_tag_t is record
203 tag : tag_number_t;
204 valid : std_ulogic;
205 end record;
206 constant instr_tag_init : instr_tag_t := (tag => 0, valid => '0');
207 function tag_match(tag1 : instr_tag_t; tag2 : instr_tag_t) return boolean;
208
209 subtype intr_vector_t is integer range 0 to 16#fff#;
210
211 -- For now, fixed 16 sources, make this either a parametric
212 -- package of some sort or an unconstrainted array.
213 type ics_to_icp_t is record
214 -- Level interrupts only, ICS just keeps prsenting the
215 -- highest priority interrupt. Once handling edge, something
216 -- smarter involving handshake & reject support will be needed
217 src : std_ulogic_vector(3 downto 0);
218 pri : std_ulogic_vector(7 downto 0);
219 end record;
220
221 -- This needs to die...
222 type ctrl_t is record
223 tb: std_ulogic_vector(63 downto 0);
224 dec: std_ulogic_vector(63 downto 0);
225 msr: std_ulogic_vector(63 downto 0);
226 cfar: std_ulogic_vector(63 downto 0);
227 xer_low: std_ulogic_vector(17 downto 0);
228 end record;
229 constant ctrl_t_init : ctrl_t :=
230 (xer_low => 18x"0", others => (others => '0'));
231
232 type Fetch1ToIcacheType is record
233 req: std_ulogic;
234 virt_mode : std_ulogic;
235 priv_mode : std_ulogic;
236 big_endian : std_ulogic;
237 stop_mark: std_ulogic;
238 predicted : std_ulogic;
239 pred_ntaken : std_ulogic;
240 nia: std_ulogic_vector(63 downto 0);
241 end record;
242
243 type IcacheToDecode1Type is record
244 valid: std_ulogic;
245 stop_mark: std_ulogic;
246 fetch_failed: std_ulogic;
247 nia: std_ulogic_vector(63 downto 0);
248 insn: std_ulogic_vector(31 downto 0);
249 icode: insn_code;
250 big_endian: std_ulogic;
251 next_predicted: std_ulogic;
252 next_pred_ntaken: std_ulogic;
253 end record;
254 constant IcacheToDecode1Init : IcacheToDecode1Type :=
255 (nia => (others => '0'), insn => (others => '0'), icode => INSN_illegal, others => '0');
256
257 type IcacheEventType is record
258 icache_miss : std_ulogic;
259 itlb_miss_resolved : std_ulogic;
260 end record;
261
262 type Decode1ToDecode2Type is record
263 valid: std_ulogic;
264 stop_mark : std_ulogic;
265 nia: std_ulogic_vector(63 downto 0);
266 prefixed: std_ulogic;
267 prefix: std_ulogic_vector(25 downto 0);
268 illegal_suffix: std_ulogic;
269 misaligned_prefix: std_ulogic;
270 insn: std_ulogic_vector(31 downto 0);
271 decode: decode_rom_t;
272 br_pred: std_ulogic; -- Branch was predicted to be taken
273 big_endian: std_ulogic;
274 spr_info : spr_id;
275 ram_spr : ram_spr_info;
276 reg_a : gspr_index_t;
277 reg_b : gspr_index_t;
278 reg_c : gspr_index_t;
279 end record;
280 constant Decode1ToDecode2Init : Decode1ToDecode2Type :=
281 (valid => '0', stop_mark => '0', nia => (others => '0'),
282 prefixed => '0', prefix => (others => '0'), insn => (others => '0'),
283 illegal_suffix => '0', misaligned_prefix => '0',
284 decode => decode_rom_init, br_pred => '0', big_endian => '0',
285 spr_info => spr_id_init, ram_spr => ram_spr_info_init,
286 reg_a => (others => '0'), reg_b => (others => '0'), reg_c => (others => '0'));
287
288 type Decode1ToFetch1Type is record
289 redirect : std_ulogic;
290 redirect_nia : std_ulogic_vector(63 downto 0);
291 end record;
292
293 type Decode1ToRegisterFileType is record
294 reg_1_addr : gspr_index_t;
295 reg_2_addr : gspr_index_t;
296 reg_3_addr : gspr_index_t;
297 read_1_enable : std_ulogic;
298 read_2_enable : std_ulogic;
299 read_3_enable : std_ulogic;
300 end record;
301
302 type bypass_data_t is record
303 tag : instr_tag_t;
304 data : std_ulogic_vector(63 downto 0);
305 end record;
306 constant bypass_data_init : bypass_data_t := (tag => instr_tag_init, data => (others => '0'));
307
308 type cr_bypass_data_t is record
309 tag : instr_tag_t;
310 data : std_ulogic_vector(31 downto 0);
311 end record;
312 constant cr_bypass_data_init : cr_bypass_data_t := (tag => instr_tag_init, data => (others => '0'));
313
314 type Decode2ToExecute1Type is record
315 valid: std_ulogic;
316 unit : unit_t;
317 fac : facility_t;
318 insn_type: insn_type_t;
319 nia: std_ulogic_vector(63 downto 0);
320 instr_tag : instr_tag_t;
321 write_reg: gspr_index_t;
322 write_reg_enable: std_ulogic;
323 read_reg1: gspr_index_t;
324 read_reg2: gspr_index_t;
325 read_reg3: gspr_index_t;
326 read_data1: std_ulogic_vector(63 downto 0);
327 read_data2: std_ulogic_vector(63 downto 0);
328 read_data3: std_ulogic_vector(63 downto 0);
329 reg_valid1: std_ulogic;
330 reg_valid2: std_ulogic;
331 reg_valid3: std_ulogic;
332 cr: std_ulogic_vector(31 downto 0);
333 xerc: xer_common_t;
334 lr: std_ulogic;
335 br_abs: std_ulogic;
336 rc: std_ulogic;
337 oe: std_ulogic;
338 invert_a: std_ulogic;
339 invert_out: std_ulogic;
340 input_carry: carry_in_t;
341 output_carry: std_ulogic;
342 input_cr: std_ulogic;
343 output_cr: std_ulogic;
344 output_xer: std_ulogic;
345 is_32bit: std_ulogic;
346 is_signed: std_ulogic;
347 insn: std_ulogic_vector(31 downto 0);
348 data_len: std_ulogic_vector(3 downto 0);
349 byte_reverse : std_ulogic;
350 sign_extend : std_ulogic; -- do we need to sign extend?
351 update : std_ulogic; -- is this an update instruction?
352 reserve : std_ulogic; -- set for larx/stcx
353 br_pred : std_ulogic;
354 result_sel : std_ulogic_vector(2 downto 0); -- select source of result
355 sub_select : std_ulogic_vector(2 downto 0); -- sub-result selection
356 repeat : std_ulogic; -- set if instruction is cracked into two ops
357 second : std_ulogic; -- set if this is the second op
358 spr_select : spr_id;
359 spr_is_ram : std_ulogic;
360 ramspr_even_rdaddr : ramspr_index;
361 ramspr_odd_rdaddr : ramspr_index;
362 ramspr_rd_odd : std_ulogic;
363 ramspr_wraddr : ramspr_index;
364 ramspr_write_even : std_ulogic;
365 ramspr_write_odd : std_ulogic;
366 dbg_spr_access : std_ulogic;
367 dec_ctr : std_ulogic;
368 prefixed : std_ulogic;
369 illegal_suffix : std_ulogic;
370 misaligned_prefix : std_ulogic;
371 end record;
372 constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
373 (valid => '0', unit => ALU, fac => NONE, insn_type => OP_ILLEGAL, instr_tag => instr_tag_init,
374 write_reg_enable => '0',
375 lr => '0', br_abs => '0', rc => '0', oe => '0', invert_a => '0',
376 invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0',
377 output_cr => '0', output_xer => '0',
378 is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0', br_pred => '0',
379 byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'),
380 read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'),
381 reg_valid1 => '0', reg_valid2 => '0', reg_valid3 => '0',
382 cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'),
383 result_sel => "000", sub_select => "000",
384 repeat => '0', second => '0', spr_select => spr_id_init,
385 spr_is_ram => '0',
386 ramspr_even_rdaddr => (others => '0'), ramspr_odd_rdaddr => (others => '0'), ramspr_rd_odd => '0',
387 ramspr_wraddr => (others => '0'), ramspr_write_even => '0', ramspr_write_odd => '0',
388 dbg_spr_access => '0',
389 dec_ctr => '0',
390 prefixed => '0', illegal_suffix => '0', misaligned_prefix => '0',
391 others => (others => '0'));
392
393 type MultiplyInputType is record
394 valid: std_ulogic;
395 data1: std_ulogic_vector(63 downto 0);
396 data2: std_ulogic_vector(63 downto 0);
397 addend: std_ulogic_vector(127 downto 0);
398 is_signed: std_ulogic;
399 subtract: std_ulogic; -- 0 => addend + data1 * data2, 1 => addend - data1 * data2
400 end record;
401 constant MultiplyInputInit : MultiplyInputType := (data1 => 64x"0", data2 => 64x"0",
402 addend => 128x"0", others => '0');
403
404 type MultiplyOutputType is record
405 valid: std_ulogic;
406 result: std_ulogic_vector(127 downto 0);
407 overflow : std_ulogic;
408 end record;
409 constant MultiplyOutputInit : MultiplyOutputType := (valid => '0', overflow => '0',
410 others => (others => '0'));
411
412 type Execute1ToDividerType is record
413 valid: std_ulogic;
414 flush: std_ulogic;
415 dividend: std_ulogic_vector(63 downto 0);
416 divisor: std_ulogic_vector(63 downto 0);
417 is_signed: std_ulogic;
418 is_32bit: std_ulogic;
419 is_extended: std_ulogic;
420 is_modulus: std_ulogic;
421 neg_result: std_ulogic;
422 end record;
423 constant Execute1ToDividerInit: Execute1ToDividerType := (
424 dividend => 64x"0", divisor => 64x"0", others => '0');
425
426 type PMUEventType is record
427 no_instr_avail : std_ulogic;
428 dispatch : std_ulogic;
429 ext_interrupt : std_ulogic;
430 instr_complete : std_ulogic;
431 fp_complete : std_ulogic;
432 ld_complete : std_ulogic;
433 st_complete : std_ulogic;
434 br_taken_complete : std_ulogic;
435 br_mispredict : std_ulogic;
436 ipref_discard : std_ulogic;
437 itlb_miss : std_ulogic;
438 itlb_miss_resolved : std_ulogic;
439 icache_miss : std_ulogic;
440 dc_miss_resolved : std_ulogic;
441 dc_load_miss : std_ulogic;
442 dc_ld_miss_resolved : std_ulogic;
443 dc_store_miss : std_ulogic;
444 dtlb_miss : std_ulogic;
445 dtlb_miss_resolved : std_ulogic;
446 ld_miss_nocache : std_ulogic;
447 ld_fill_nocache : std_ulogic;
448 end record;
449 constant PMUEventInit : PMUEventType := (others => '0');
450
451 type Execute1ToPMUType is record
452 mfspr : std_ulogic;
453 mtspr : std_ulogic;
454 spr_num : std_ulogic_vector(4 downto 0);
455 spr_val : std_ulogic_vector(63 downto 0);
456 tbbits : std_ulogic_vector(3 downto 0); -- event bits from timebase
457 pmm_msr : std_ulogic; -- PMM bit from MSR
458 pr_msr : std_ulogic; -- PR bit from MSR
459 run : std_ulogic;
460 nia : std_ulogic_vector(63 downto 0);
461 addr : std_ulogic_vector(63 downto 0);
462 addr_v : std_ulogic;
463 occur : PMUEventType;
464 end record;
465
466 type PMUToExecute1Type is record
467 spr_val : std_ulogic_vector(63 downto 0);
468 intr : std_ulogic;
469 end record;
470
471 type Decode2ToRegisterFileType is record
472 read1_enable : std_ulogic;
473 read2_enable : std_ulogic;
474 read3_enable : std_ulogic;
475 end record;
476
477 type RegisterFileToDecode2Type is record
478 read1_data : std_ulogic_vector(63 downto 0);
479 read2_data : std_ulogic_vector(63 downto 0);
480 read3_data : std_ulogic_vector(63 downto 0);
481 end record;
482
483 type Decode2ToCrFileType is record
484 read : std_ulogic;
485 end record;
486
487 type CrFileToDecode2Type is record
488 read_cr_data : std_ulogic_vector(31 downto 0);
489 read_xerc_data : xer_common_t;
490 end record;
491
492 type Execute1ToLoadstore1Type is record
493 valid : std_ulogic;
494 op : insn_type_t; -- what ld/st or m[tf]spr or TLB op to do
495 insn : std_ulogic_vector(31 downto 0);
496 instr_tag : instr_tag_t;
497 addr1 : std_ulogic_vector(63 downto 0);
498 addr2 : std_ulogic_vector(63 downto 0);
499 data : std_ulogic_vector(63 downto 0); -- data to write, unused for read
500 write_reg : gspr_index_t;
501 length : std_ulogic_vector(3 downto 0);
502 ci : std_ulogic; -- cache-inhibited load/store
503 byte_reverse : std_ulogic;
504 sign_extend : std_ulogic; -- do we need to sign extend?
505 update : std_ulogic; -- is this an update instruction?
506 xerc : xer_common_t;
507 reserve : std_ulogic; -- set for larx/stcx.
508 rc : std_ulogic; -- set for stcx.
509 virt_mode : std_ulogic; -- do translation through TLB
510 priv_mode : std_ulogic; -- privileged mode (MSR[PR] = 0)
511 mode_32bit : std_ulogic; -- trim addresses to 32 bits
512 is_32bit : std_ulogic;
513 prefixed : std_ulogic;
514 repeat : std_ulogic;
515 second : std_ulogic;
516 e2stall : std_ulogic;
517 msr : std_ulogic_vector(63 downto 0);
518 end record;
519 constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type :=
520 (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
521 sign_extend => '0', update => '0', xerc => xerc_init,
522 reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
523 insn => (others => '0'),
524 instr_tag => instr_tag_init,
525 addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'),
526 write_reg => (others => '0'),
527 length => (others => '0'),
528 mode_32bit => '0', is_32bit => '0', prefixed => '0',
529 repeat => '0', second => '0', e2stall => '0',
530 msr => (others => '0'));
531
532 type Loadstore1ToExecute1Type is record
533 busy : std_ulogic;
534 l2stall : std_ulogic;
535 end record;
536
537 type Loadstore1ToDcacheType is record
538 valid : std_ulogic;
539 hold : std_ulogic;
540 load : std_ulogic; -- is this a load
541 dcbz : std_ulogic;
542 nc : std_ulogic;
543 reserve : std_ulogic;
544 virt_mode : std_ulogic;
545 priv_mode : std_ulogic;
546 addr : std_ulogic_vector(63 downto 0);
547 data : std_ulogic_vector(63 downto 0); -- valid the cycle after .valid = 1
548 byte_sel : std_ulogic_vector(7 downto 0);
549 end record;
550
551 type DcacheToLoadstore1Type is record
552 valid : std_ulogic;
553 data : std_ulogic_vector(63 downto 0);
554 store_done : std_ulogic;
555 error : std_ulogic;
556 cache_paradox : std_ulogic;
557 end record;
558
559 type DcacheEventType is record
560 load_miss : std_ulogic;
561 store_miss : std_ulogic;
562 dcache_refill : std_ulogic;
563 dtlb_miss : std_ulogic;
564 dtlb_miss_resolved : std_ulogic;
565 end record;
566
567 type Loadstore1ToMmuType is record
568 valid : std_ulogic;
569 tlbie : std_ulogic;
570 slbia : std_ulogic;
571 mtspr : std_ulogic;
572 iside : std_ulogic;
573 load : std_ulogic;
574 priv : std_ulogic;
575 ric : std_ulogic_vector(1 downto 0);
576 sprnf : std_ulogic;
577 sprnt : std_ulogic;
578 addr : std_ulogic_vector(63 downto 0);
579 rs : std_ulogic_vector(63 downto 0);
580 end record;
581
582 type MmuToLoadstore1Type is record
583 done : std_ulogic;
584 err : std_ulogic;
585 invalid : std_ulogic;
586 badtree : std_ulogic;
587 segerr : std_ulogic;
588 perm_error : std_ulogic;
589 rc_error : std_ulogic;
590 sprval : std_ulogic_vector(63 downto 0);
591 end record;
592
593 type MmuToDcacheType is record
594 valid : std_ulogic;
595 tlbie : std_ulogic;
596 doall : std_ulogic;
597 tlbld : std_ulogic;
598 addr : std_ulogic_vector(63 downto 0);
599 pte : std_ulogic_vector(63 downto 0);
600 end record;
601
602 type DcacheToMmuType is record
603 stall : std_ulogic;
604 done : std_ulogic;
605 err : std_ulogic;
606 data : std_ulogic_vector(63 downto 0);
607 end record;
608
609 type MmuToIcacheType is record
610 tlbld : std_ulogic;
611 tlbie : std_ulogic;
612 doall : std_ulogic;
613 addr : std_ulogic_vector(63 downto 0);
614 pte : std_ulogic_vector(63 downto 0);
615 end record;
616
617 type Loadstore1ToWritebackType is record
618 valid : std_ulogic;
619 instr_tag : instr_tag_t;
620 write_enable: std_ulogic;
621 write_reg : gspr_index_t;
622 write_data : std_ulogic_vector(63 downto 0);
623 xerc : xer_common_t;
624 rc : std_ulogic;
625 store_done : std_ulogic;
626 interrupt : std_ulogic;
627 intr_vec : intr_vector_t;
628 srr1: std_ulogic_vector(15 downto 0);
629 end record;
630 constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType :=
631 (valid => '0', instr_tag => instr_tag_init, write_enable => '0',
632 write_reg => (others => '0'), write_data => (others => '0'),
633 xerc => xerc_init, rc => '0', store_done => '0',
634 interrupt => '0', intr_vec => 0,
635 srr1 => (others => '0'));
636
637 type Loadstore1EventType is record
638 load_complete : std_ulogic;
639 store_complete : std_ulogic;
640 itlb_miss : std_ulogic;
641 end record;
642
643 type Execute1ToWritebackType is record
644 valid: std_ulogic;
645 instr_tag : instr_tag_t;
646 rc : std_ulogic;
647 mode_32bit : std_ulogic;
648 write_enable : std_ulogic;
649 write_reg: gspr_index_t;
650 write_data: std_ulogic_vector(63 downto 0);
651 write_cr_enable : std_ulogic;
652 write_cr_mask : std_ulogic_vector(7 downto 0);
653 write_cr_data : std_ulogic_vector(31 downto 0);
654 write_xerc_enable : std_ulogic;
655 xerc : xer_common_t;
656 interrupt : std_ulogic;
657 intr_vec : intr_vector_t;
658 redirect: std_ulogic;
659 redir_mode: std_ulogic_vector(3 downto 0);
660 last_nia: std_ulogic_vector(63 downto 0);
661 br_offset: std_ulogic_vector(63 downto 0);
662 br_last: std_ulogic;
663 br_taken: std_ulogic;
664 abs_br: std_ulogic;
665 srr1: std_ulogic_vector(15 downto 0);
666 msr: std_ulogic_vector(63 downto 0);
667 end record;
668 constant Execute1ToWritebackInit : Execute1ToWritebackType :=
669 (valid => '0', instr_tag => instr_tag_init, rc => '0', mode_32bit => '0',
670 write_enable => '0', write_cr_enable => '0',
671 write_xerc_enable => '0', xerc => xerc_init,
672 write_data => (others => '0'), write_cr_mask => (others => '0'),
673 write_cr_data => (others => '0'), write_reg => (others => '0'),
674 interrupt => '0', intr_vec => 0, redirect => '0', redir_mode => "0000",
675 last_nia => (others => '0'), br_offset => (others => '0'),
676 br_last => '0', br_taken => '0', abs_br => '0',
677 srr1 => (others => '0'), msr => (others => '0'));
678
679 type Execute1ToFPUType is record
680 valid : std_ulogic;
681 op : insn_type_t;
682 nia : std_ulogic_vector(63 downto 0);
683 itag : instr_tag_t;
684 insn : std_ulogic_vector(31 downto 0);
685 single : std_ulogic;
686 is_signed : std_ulogic;
687 fe_mode : std_ulogic_vector(1 downto 0);
688 fra : std_ulogic_vector(63 downto 0);
689 frb : std_ulogic_vector(63 downto 0);
690 frc : std_ulogic_vector(63 downto 0);
691 valid_a : std_ulogic;
692 valid_b : std_ulogic;
693 valid_c : std_ulogic;
694 frt : gspr_index_t;
695 rc : std_ulogic;
696 m32b : std_ulogic;
697 out_cr : std_ulogic;
698 oe : std_ulogic;
699 xerc : xer_common_t;
700 stall : std_ulogic;
701 end record;
702 constant Execute1ToFPUInit : Execute1ToFPUType := (valid => '0', op => OP_ILLEGAL, nia => (others => '0'),
703 itag => instr_tag_init,
704 insn => (others => '0'), fe_mode => "00", rc => '0',
705 fra => (others => '0'), frb => (others => '0'),
706 frc => (others => '0'), frt => (others => '0'),
707 valid_a => '0', valid_b => '0', valid_c => '0',
708 single => '0', is_signed => '0', out_cr => '0',
709 m32b => '0', oe => '0', xerc => xerc_init,
710 stall => '0');
711
712 type FPUToExecute1Type is record
713 busy : std_ulogic;
714 f2stall : std_ulogic;
715 exception : std_ulogic;
716 end record;
717 constant FPUToExecute1Init : FPUToExecute1Type := (others => '0');
718
719 type FPUToWritebackType is record
720 valid : std_ulogic;
721 interrupt : std_ulogic;
722 instr_tag : instr_tag_t;
723 write_enable : std_ulogic;
724 write_reg : gspr_index_t;
725 write_data : std_ulogic_vector(63 downto 0);
726 write_cr_enable : std_ulogic;
727 write_cr_mask : std_ulogic_vector(7 downto 0);
728 write_cr_data : std_ulogic_vector(31 downto 0);
729 write_xerc : std_ulogic;
730 xerc : xer_common_t;
731 intr_vec : intr_vector_t;
732 srr1 : std_ulogic_vector(15 downto 0);
733 end record;
734 constant FPUToWritebackInit : FPUToWritebackType :=
735 (valid => '0', interrupt => '0', instr_tag => instr_tag_init,
736 write_enable => '0', write_reg => (others => '0'),
737 write_cr_enable => '0', write_cr_mask => (others => '0'),
738 write_cr_data => (others => '0'),
739 write_xerc => '0', xerc => xerc_init,
740 intr_vec => 0, srr1 => (others => '0'),
741 others => (others => '0'));
742
743 type DividerToExecute1Type is record
744 valid: std_ulogic;
745 write_reg_data: std_ulogic_vector(63 downto 0);
746 overflow : std_ulogic;
747 end record;
748 constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
749 others => (others => '0'));
750
751 type WritebackToFetch1Type is record
752 redirect: std_ulogic;
753 virt_mode: std_ulogic;
754 priv_mode: std_ulogic;
755 big_endian: std_ulogic;
756 mode_32bit: std_ulogic;
757 redirect_nia: std_ulogic_vector(63 downto 0);
758 br_nia : std_ulogic_vector(63 downto 0);
759 br_last : std_ulogic;
760 br_taken : std_ulogic;
761 end record;
762 constant WritebackToFetch1Init : WritebackToFetch1Type :=
763 (redirect => '0', virt_mode => '0', priv_mode => '0', big_endian => '0',
764 mode_32bit => '0', redirect_nia => (others => '0'),
765 br_last => '0', br_taken => '0', br_nia => (others => '0'));
766
767 type WritebackToRegisterFileType is record
768 write_reg : gspr_index_t;
769 write_data : std_ulogic_vector(63 downto 0);
770 write_enable : std_ulogic;
771 end record;
772 constant WritebackToRegisterFileInit : WritebackToRegisterFileType :=
773 (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
774
775 type WritebackToCrFileType is record
776 write_cr_enable : std_ulogic;
777 write_cr_mask : std_ulogic_vector(7 downto 0);
778 write_cr_data : std_ulogic_vector(31 downto 0);
779 write_xerc_enable : std_ulogic;
780 write_xerc_data : xer_common_t;
781 end record;
782 constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
783 write_xerc_data => xerc_init,
784 write_cr_mask => (others => '0'),
785 write_cr_data => (others => '0'));
786
787 type WritebackToExecute1Type is record
788 intr : std_ulogic;
789 srr1 : std_ulogic_vector(15 downto 0);
790 end record;
791
792 type WritebackEventType is record
793 instr_complete : std_ulogic;
794 fp_complete : std_ulogic;
795 end record;
796
797 end common;
798
799 package body common is
800 function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
801 begin
802 return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
803 end;
804
805 function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
806 begin
807 return i(4 downto 0);
808 end;
809
810 function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
811 begin
812 return "0" & i;
813 end;
814
815 function fpr_to_gspr(f: fpr_index_t) return gspr_index_t is
816 begin
817 return "1" & f;
818 end;
819
820 function tag_match(tag1 : instr_tag_t; tag2 : instr_tag_t) return boolean is
821 begin
822 return tag1.valid = '1' and tag2.valid = '1' and tag1.tag = tag2.tag;
823 end;
824
825 function addr_to_real(addr: std_ulogic_vector(63 downto 0)) return real_addr_t is
826 begin
827 return addr(real_addr_t'range);
828 end;
829 end common;