2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 use work.decode_types.all;
10 -- Processor Version Number
11 constant PVR_MICROWATT : std_ulogic_vector(31 downto 0) := x"00630000";
14 constant MSR_SF : integer := (63 - 0); -- Sixty-Four bit mode
15 constant MSR_EE : integer := (63 - 48); -- External interrupt Enable
16 constant MSR_PR : integer := (63 - 49); -- PRoblem state
17 constant MSR_FP : integer := (63 - 50); -- Floating Point available
18 constant MSR_FE0 : integer := (63 - 52); -- Floating Exception mode
19 constant MSR_SE : integer := (63 - 53); -- Single-step bit of TE field
20 constant MSR_BE : integer := (63 - 54); -- Branch trace bit of TE field
21 constant MSR_FE1 : integer := (63 - 55); -- Floating Exception mode
22 constant MSR_IR : integer := (63 - 58); -- Instruction Relocation
23 constant MSR_DR : integer := (63 - 59); -- Data Relocation
24 constant MSR_RI : integer := (63 - 62); -- Recoverable Interrupt
25 constant MSR_LE : integer := (63 - 63); -- Little Endian
28 subtype spr_num_t is integer range 0 to 1023;
30 function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
32 constant SPR_XER : spr_num_t := 1;
33 constant SPR_LR : spr_num_t := 8;
34 constant SPR_CTR : spr_num_t := 9;
35 constant SPR_TAR : spr_num_t := 815;
36 constant SPR_DSISR : spr_num_t := 18;
37 constant SPR_DAR : spr_num_t := 19;
38 constant SPR_TB : spr_num_t := 268;
39 constant SPR_TBU : spr_num_t := 269;
40 constant SPR_DEC : spr_num_t := 22;
41 constant SPR_SRR0 : spr_num_t := 26;
42 constant SPR_SRR1 : spr_num_t := 27;
43 constant SPR_CFAR : spr_num_t := 28;
44 constant SPR_HSRR0 : spr_num_t := 314;
45 constant SPR_HSRR1 : spr_num_t := 315;
46 constant SPR_SPRG0 : spr_num_t := 272;
47 constant SPR_SPRG1 : spr_num_t := 273;
48 constant SPR_SPRG2 : spr_num_t := 274;
49 constant SPR_SPRG3 : spr_num_t := 275;
50 constant SPR_SPRG3U : spr_num_t := 259;
51 constant SPR_HSPRG0 : spr_num_t := 304;
52 constant SPR_HSPRG1 : spr_num_t := 305;
53 constant SPR_PID : spr_num_t := 48;
54 constant SPR_PRTBL : spr_num_t := 720;
55 constant SPR_PVR : spr_num_t := 287;
57 -- GPR indices in the register file (GPR only)
58 subtype gpr_index_t is std_ulogic_vector(4 downto 0);
60 -- Extended GPR index (can hold an SPR or a FPR)
61 subtype gspr_index_t is std_ulogic_vector(6 downto 0);
64 subtype fpr_index_t is std_ulogic_vector(4 downto 0);
66 -- Some SPRs are stored in the register file, they use the magic
67 -- GPR numbers above 31.
69 -- The function fast_spr_num() returns the corresponding fast
70 -- pseudo-GPR number for a given SPR number. The result MSB
71 -- indicates if this is indeed a fast SPR. If clear, then
72 -- the SPR is not stored in the GPR file.
74 -- FPRs are also stored in the register file, using GSPR
75 -- numbers from 64 to 95.
77 function fast_spr_num(spr: spr_num_t) return gspr_index_t;
79 -- Indices conversion functions
80 function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
81 function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
82 function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
83 function is_fast_spr(s: gspr_index_t) return std_ulogic;
84 function fpr_to_gspr(f: fpr_index_t) return gspr_index_t;
86 -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
87 -- in the CR file as a kind of CR extension (with a separate write
88 -- control). The rest is stored as a fast SPR.
89 type xer_common_t is record
96 constant xerc_init : xer_common_t := (others => '0');
99 constant FPSCR_FX : integer := 63 - 32;
100 constant FPSCR_FEX : integer := 63 - 33;
101 constant FPSCR_VX : integer := 63 - 34;
102 constant FPSCR_OX : integer := 63 - 35;
103 constant FPSCR_UX : integer := 63 - 36;
104 constant FPSCR_ZX : integer := 63 - 37;
105 constant FPSCR_XX : integer := 63 - 38;
106 constant FPSCR_VXSNAN : integer := 63 - 39;
107 constant FPSCR_VXISI : integer := 63 - 40;
108 constant FPSCR_VXIDI : integer := 63 - 41;
109 constant FPSCR_VXZDZ : integer := 63 - 42;
110 constant FPSCR_VXIMZ : integer := 63 - 43;
111 constant FPSCR_VXVC : integer := 63 - 44;
112 constant FPSCR_FR : integer := 63 - 45;
113 constant FPSCR_FI : integer := 63 - 46;
114 constant FPSCR_C : integer := 63 - 47;
115 constant FPSCR_FL : integer := 63 - 48;
116 constant FPSCR_FG : integer := 63 - 49;
117 constant FPSCR_FE : integer := 63 - 50;
118 constant FPSCR_FU : integer := 63 - 51;
119 constant FPSCR_VXSOFT : integer := 63 - 53;
120 constant FPSCR_VXSQRT : integer := 63 - 54;
121 constant FPSCR_VXCVI : integer := 63 - 55;
122 constant FPSCR_VE : integer := 63 - 56;
123 constant FPSCR_OE : integer := 63 - 57;
124 constant FPSCR_UE : integer := 63 - 58;
125 constant FPSCR_ZE : integer := 63 - 59;
126 constant FPSCR_XE : integer := 63 - 60;
127 constant FPSCR_NI : integer := 63 - 61;
128 constant FPSCR_RN : integer := 63 - 63;
130 -- Used for tracking instruction completion and pending register writes
131 constant TAG_COUNT : positive := 4;
132 constant TAG_NUMBER_BITS : natural := log2(TAG_COUNT);
133 subtype tag_number_t is integer range 0 to TAG_COUNT - 1;
134 subtype tag_index_t is unsigned(TAG_NUMBER_BITS - 1 downto 0);
135 type instr_tag_t is record
139 constant instr_tag_init : instr_tag_t := (tag => 0, valid => '0');
140 function tag_match(tag1 : instr_tag_t; tag2 : instr_tag_t) return boolean;
142 subtype intr_vector_t is integer range 0 to 16#fff#;
144 -- For now, fixed 16 sources, make this either a parametric
145 -- package of some sort or an unconstrainted array.
146 type ics_to_icp_t is record
147 -- Level interrupts only, ICS just keeps prsenting the
148 -- highest priority interrupt. Once handling edge, something
149 -- smarter involving handshake & reject support will be needed
150 src : std_ulogic_vector(3 downto 0);
151 pri : std_ulogic_vector(7 downto 0);
154 -- This needs to die...
155 type ctrl_t is record
156 tb: std_ulogic_vector(63 downto 0);
157 dec: std_ulogic_vector(63 downto 0);
158 msr: std_ulogic_vector(63 downto 0);
159 cfar: std_ulogic_vector(63 downto 0);
162 type Fetch1ToIcacheType is record
164 virt_mode : std_ulogic;
165 priv_mode : std_ulogic;
166 big_endian : std_ulogic;
167 stop_mark: std_ulogic;
168 sequential: std_ulogic;
169 predicted : std_ulogic;
170 nia: std_ulogic_vector(63 downto 0);
173 type IcacheToDecode1Type is record
175 stop_mark: std_ulogic;
176 fetch_failed: std_ulogic;
177 nia: std_ulogic_vector(63 downto 0);
178 insn: std_ulogic_vector(31 downto 0);
179 big_endian: std_ulogic;
180 next_predicted: std_ulogic;
183 type Decode1ToDecode2Type is record
185 stop_mark : std_ulogic;
186 nia: std_ulogic_vector(63 downto 0);
187 insn: std_ulogic_vector(31 downto 0);
188 ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
189 ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
190 ispro: gspr_index_t; -- (G)SPR written with LR or CTR
191 decode: decode_rom_t;
192 br_pred: std_ulogic; -- Branch was predicted to be taken
193 big_endian: std_ulogic;
195 constant Decode1ToDecode2Init : Decode1ToDecode2Type :=
196 (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'),
197 ispr1 => (others => '0'), ispr2 => (others => '0'), ispro => (others => '0'),
198 decode => decode_rom_init, br_pred => '0', big_endian => '0');
200 type Decode1ToFetch1Type is record
201 redirect : std_ulogic;
202 redirect_nia : std_ulogic_vector(63 downto 0);
205 type bypass_data_t is record
207 data : std_ulogic_vector(63 downto 0);
209 constant bypass_data_init : bypass_data_t := (tag => instr_tag_init, data => (others => '0'));
211 type cr_bypass_data_t is record
213 data : std_ulogic_vector(31 downto 0);
215 constant cr_bypass_data_init : cr_bypass_data_t := (tag => instr_tag_init, data => (others => '0'));
217 type Decode2ToExecute1Type is record
221 insn_type: insn_type_t;
222 nia: std_ulogic_vector(63 downto 0);
223 instr_tag : instr_tag_t;
224 write_reg: gspr_index_t;
225 write_reg_enable: std_ulogic;
226 read_reg1: gspr_index_t;
227 read_reg2: gspr_index_t;
228 read_data1: std_ulogic_vector(63 downto 0);
229 read_data2: std_ulogic_vector(63 downto 0);
230 read_data3: std_ulogic_vector(63 downto 0);
231 cr: std_ulogic_vector(31 downto 0);
237 invert_a: std_ulogic;
239 invert_out: std_ulogic;
240 input_carry: carry_in_t;
241 output_carry: std_ulogic;
242 input_cr: std_ulogic;
243 output_cr: std_ulogic;
244 output_xer: std_ulogic;
245 is_32bit: std_ulogic;
246 is_signed: std_ulogic;
247 insn: std_ulogic_vector(31 downto 0);
248 data_len: std_ulogic_vector(3 downto 0);
249 byte_reverse : std_ulogic;
250 sign_extend : std_ulogic; -- do we need to sign extend?
251 update : std_ulogic; -- is this an update instruction?
252 reserve : std_ulogic; -- set for larx/stcx
253 br_pred : std_ulogic;
254 result_sel : std_ulogic_vector(2 downto 0); -- select source of result
255 sub_select : std_ulogic_vector(2 downto 0); -- sub-result selection
256 repeat : std_ulogic; -- set if instruction is cracked into two ops
257 second : std_ulogic; -- set if this is the second op
259 constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
260 (valid => '0', unit => NONE, fac => NONE, insn_type => OP_ILLEGAL, instr_tag => instr_tag_init,
261 write_reg_enable => '0',
262 lr => '0', br_abs => '0', rc => '0', oe => '0', invert_a => '0', addm1 => '0',
263 invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0',
264 output_cr => '0', output_xer => '0',
265 is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0', br_pred => '0',
266 byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'),
267 read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'),
268 cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'),
269 result_sel => "000", sub_select => "000",
270 repeat => '0', second => '0', others => (others => '0'));
272 type MultiplyInputType is record
274 data1: std_ulogic_vector(63 downto 0);
275 data2: std_ulogic_vector(63 downto 0);
276 addend: std_ulogic_vector(127 downto 0);
277 is_32bit: std_ulogic;
278 not_result: std_ulogic;
280 constant MultiplyInputInit : MultiplyInputType := (valid => '0',
281 is_32bit => '0', not_result => '0',
282 others => (others => '0'));
284 type MultiplyOutputType is record
286 result: std_ulogic_vector(127 downto 0);
287 overflow : std_ulogic;
289 constant MultiplyOutputInit : MultiplyOutputType := (valid => '0', overflow => '0',
290 others => (others => '0'));
292 type Execute1ToDividerType is record
294 dividend: std_ulogic_vector(63 downto 0);
295 divisor: std_ulogic_vector(63 downto 0);
296 is_signed: std_ulogic;
297 is_32bit: std_ulogic;
298 is_extended: std_ulogic;
299 is_modulus: std_ulogic;
300 neg_result: std_ulogic;
302 constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
303 is_extended => '0', is_modulus => '0',
304 neg_result => '0', others => (others => '0'));
306 type Decode2ToRegisterFileType is record
307 read1_enable : std_ulogic;
308 read1_reg : gspr_index_t;
309 read2_enable : std_ulogic;
310 read2_reg : gspr_index_t;
311 read3_enable : std_ulogic;
312 read3_reg : gspr_index_t;
315 type RegisterFileToDecode2Type is record
316 read1_data : std_ulogic_vector(63 downto 0);
317 read2_data : std_ulogic_vector(63 downto 0);
318 read3_data : std_ulogic_vector(63 downto 0);
321 type Decode2ToCrFileType is record
325 type CrFileToDecode2Type is record
326 read_cr_data : std_ulogic_vector(31 downto 0);
327 read_xerc_data : xer_common_t;
330 type Execute1ToLoadstore1Type is record
332 op : insn_type_t; -- what ld/st or m[tf]spr or TLB op to do
333 nia : std_ulogic_vector(63 downto 0);
334 insn : std_ulogic_vector(31 downto 0);
335 instr_tag : instr_tag_t;
336 addr1 : std_ulogic_vector(63 downto 0);
337 addr2 : std_ulogic_vector(63 downto 0);
338 data : std_ulogic_vector(63 downto 0); -- data to write, unused for read
339 write_reg : gspr_index_t;
340 length : std_ulogic_vector(3 downto 0);
341 ci : std_ulogic; -- cache-inhibited load/store
342 byte_reverse : std_ulogic;
343 sign_extend : std_ulogic; -- do we need to sign extend?
344 update : std_ulogic; -- is this an update instruction?
346 reserve : std_ulogic; -- set for larx/stcx.
347 rc : std_ulogic; -- set for stcx.
348 virt_mode : std_ulogic; -- do translation through TLB
349 priv_mode : std_ulogic; -- privileged mode (MSR[PR] = 0)
350 mode_32bit : std_ulogic; -- trim addresses to 32 bits
351 is_32bit : std_ulogic;
354 msr : std_ulogic_vector(63 downto 0);
356 constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type :=
357 (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
358 sign_extend => '0', update => '0', xerc => xerc_init,
359 reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
360 nia => (others => '0'), insn => (others => '0'),
361 instr_tag => instr_tag_init,
362 addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'),
363 write_reg => (others => '0'),
364 length => (others => '0'),
365 mode_32bit => '0', is_32bit => '0',
366 repeat => '0', second => '0',
367 msr => (others => '0'));
369 type Loadstore1ToExecute1Type is record
371 in_progress : std_ulogic;
374 type Loadstore1ToDcacheType is record
377 load : std_ulogic; -- is this a load
380 reserve : std_ulogic;
381 atomic : std_ulogic; -- part of a multi-transfer atomic op
382 atomic_last : std_ulogic;
383 virt_mode : std_ulogic;
384 priv_mode : std_ulogic;
385 addr : std_ulogic_vector(63 downto 0);
386 data : std_ulogic_vector(63 downto 0); -- valid the cycle after .valid = 1
387 byte_sel : std_ulogic_vector(7 downto 0);
390 type DcacheToLoadstore1Type is record
392 data : std_ulogic_vector(63 downto 0);
393 store_done : std_ulogic;
395 cache_paradox : std_ulogic;
398 type Loadstore1ToMmuType is record
406 sprn : std_ulogic_vector(9 downto 0);
407 addr : std_ulogic_vector(63 downto 0);
408 rs : std_ulogic_vector(63 downto 0);
411 type MmuToLoadstore1Type is record
414 invalid : std_ulogic;
415 badtree : std_ulogic;
417 perm_error : std_ulogic;
418 rc_error : std_ulogic;
419 sprval : std_ulogic_vector(63 downto 0);
422 type MmuToDcacheType is record
427 addr : std_ulogic_vector(63 downto 0);
428 pte : std_ulogic_vector(63 downto 0);
431 type DcacheToMmuType is record
435 data : std_ulogic_vector(63 downto 0);
438 type MmuToIcacheType is record
442 addr : std_ulogic_vector(63 downto 0);
443 pte : std_ulogic_vector(63 downto 0);
446 type Loadstore1ToWritebackType is record
448 instr_tag : instr_tag_t;
449 write_enable: std_ulogic;
450 write_reg : gspr_index_t;
451 write_data : std_ulogic_vector(63 downto 0);
454 store_done : std_ulogic;
455 interrupt : std_ulogic;
456 intr_vec : intr_vector_t;
457 srr0: std_ulogic_vector(63 downto 0);
458 srr1: std_ulogic_vector(15 downto 0);
460 constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType :=
461 (valid => '0', instr_tag => instr_tag_init, write_enable => '0',
462 write_reg => (others => '0'), write_data => (others => '0'),
463 xerc => xerc_init, rc => '0', store_done => '0',
464 interrupt => '0', intr_vec => 0,
465 srr0 => (others => '0'), srr1 => (others => '0'));
467 type Execute1ToWritebackType is record
469 instr_tag : instr_tag_t;
471 mode_32bit : std_ulogic;
472 write_enable : std_ulogic;
473 write_reg: gspr_index_t;
474 write_data: std_ulogic_vector(63 downto 0);
475 write_cr_enable : std_ulogic;
476 write_cr_mask : std_ulogic_vector(7 downto 0);
477 write_cr_data : std_ulogic_vector(31 downto 0);
478 write_xerc_enable : std_ulogic;
480 interrupt : std_ulogic;
481 intr_vec : intr_vector_t;
482 redirect: std_ulogic;
483 redir_mode: std_ulogic_vector(3 downto 0);
484 last_nia: std_ulogic_vector(63 downto 0);
485 br_offset: std_ulogic_vector(63 downto 0);
487 br_taken: std_ulogic;
489 srr1: std_ulogic_vector(15 downto 0);
490 msr: std_ulogic_vector(63 downto 0);
492 constant Execute1ToWritebackInit : Execute1ToWritebackType :=
493 (valid => '0', instr_tag => instr_tag_init, rc => '0', mode_32bit => '0',
494 write_enable => '0', write_cr_enable => '0',
495 write_xerc_enable => '0', xerc => xerc_init,
496 write_data => (others => '0'), write_cr_mask => (others => '0'),
497 write_cr_data => (others => '0'), write_reg => (others => '0'),
498 interrupt => '0', intr_vec => 0, redirect => '0', redir_mode => "0000",
499 last_nia => (others => '0'), br_offset => (others => '0'),
500 br_last => '0', br_taken => '0', abs_br => '0',
501 srr1 => (others => '0'), msr => (others => '0'));
503 type Execute1ToFPUType is record
506 nia : std_ulogic_vector(63 downto 0);
508 insn : std_ulogic_vector(31 downto 0);
510 fe_mode : std_ulogic_vector(1 downto 0);
511 fra : std_ulogic_vector(63 downto 0);
512 frb : std_ulogic_vector(63 downto 0);
513 frc : std_ulogic_vector(63 downto 0);
518 constant Execute1ToFPUInit : Execute1ToFPUType := (valid => '0', op => OP_ILLEGAL, nia => (others => '0'),
519 itag => instr_tag_init,
520 insn => (others => '0'), fe_mode => "00", rc => '0',
521 fra => (others => '0'), frb => (others => '0'),
522 frc => (others => '0'), frt => (others => '0'),
523 single => '0', out_cr => '0');
525 type FPUToExecute1Type is record
527 exception : std_ulogic;
529 constant FPUToExecute1Init : FPUToExecute1Type := (others => '0');
531 type FPUToWritebackType is record
533 interrupt : std_ulogic;
534 instr_tag : instr_tag_t;
535 write_enable : std_ulogic;
536 write_reg : gspr_index_t;
537 write_data : std_ulogic_vector(63 downto 0);
538 write_cr_enable : std_ulogic;
539 write_cr_mask : std_ulogic_vector(7 downto 0);
540 write_cr_data : std_ulogic_vector(31 downto 0);
541 intr_vec : intr_vector_t;
542 srr0 : std_ulogic_vector(63 downto 0);
543 srr1 : std_ulogic_vector(15 downto 0);
545 constant FPUToWritebackInit : FPUToWritebackType :=
546 (valid => '0', interrupt => '0', instr_tag => instr_tag_init,
547 write_enable => '0', write_reg => (others => '0'),
548 write_cr_enable => '0', write_cr_mask => (others => '0'),
549 write_cr_data => (others => '0'),
550 intr_vec => 0, srr1 => (others => '0'),
551 others => (others => '0'));
553 type DividerToExecute1Type is record
555 write_reg_data: std_ulogic_vector(63 downto 0);
556 overflow : std_ulogic;
558 constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
559 others => (others => '0'));
561 type WritebackToFetch1Type is record
562 redirect: std_ulogic;
563 virt_mode: std_ulogic;
564 priv_mode: std_ulogic;
565 big_endian: std_ulogic;
566 mode_32bit: std_ulogic;
567 redirect_nia: std_ulogic_vector(63 downto 0);
568 br_nia : std_ulogic_vector(63 downto 0);
569 br_last : std_ulogic;
570 br_taken : std_ulogic;
572 constant WritebackToFetch1Init : WritebackToFetch1Type :=
573 (redirect => '0', virt_mode => '0', priv_mode => '0', big_endian => '0',
574 mode_32bit => '0', redirect_nia => (others => '0'),
575 br_last => '0', br_taken => '0', br_nia => (others => '0'));
577 type WritebackToRegisterFileType is record
578 write_reg : gspr_index_t;
579 write_data : std_ulogic_vector(63 downto 0);
580 write_enable : std_ulogic;
582 constant WritebackToRegisterFileInit : WritebackToRegisterFileType :=
583 (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
585 type WritebackToCrFileType is record
586 write_cr_enable : std_ulogic;
587 write_cr_mask : std_ulogic_vector(7 downto 0);
588 write_cr_data : std_ulogic_vector(31 downto 0);
589 write_xerc_enable : std_ulogic;
590 write_xerc_data : xer_common_t;
592 constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
593 write_xerc_data => xerc_init,
594 write_cr_mask => (others => '0'),
595 write_cr_data => (others => '0'));
599 package body common is
600 function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
602 return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
604 function fast_spr_num(spr: spr_num_t) return gspr_index_t is
605 variable n : integer range 0 to 31;
606 -- tmp variable introduced as workaround for VCS compilation
607 -- simulation was failing with subtype constraint mismatch error
608 -- see GitHub PR #173
609 variable tmp : std_ulogic_vector(4 downto 0);
613 n := 0; -- N.B. decode2 relies on this specific value
615 n := 1; -- N.B. decode2 relies on this specific value
630 when SPR_SPRG3 | SPR_SPRG3U =>
644 tmp := std_ulogic_vector(to_unsigned(n, 5));
648 function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
650 return i(4 downto 0);
653 function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
658 function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
663 return gpr_to_gspr(g);
667 function is_fast_spr(s: gspr_index_t) return std_ulogic is
672 function fpr_to_gspr(f: fpr_index_t) return gspr_index_t is
677 function tag_match(tag1 : instr_tag_t; tag2 : instr_tag_t) return boolean is
679 return tag1.valid = '1' and tag2.valid = '1' and tag1.tag = tag2.tag;