common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7
   8 package common is
   9     -- Processor Version Number
  10     constant PVR_MICROWATT  : std_ulogic_vector(31 downto 0) := x"00630000";
  11
  12     -- MSR bit numbers
  13     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  14     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  15     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  16     constant MSR_SE  : integer := (63 - 53);    -- Single-step bit of TE field
  17     constant MSR_BE  : integer := (63 - 54);    -- Branch trace bit of TE field
  18     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  19     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  20     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  21     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  22
  23     -- SPR numbers
  24     subtype spr_num_t is integer range 0 to 1023;
  25
  26     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  27
  28     constant SPR_XER    : spr_num_t := 1;
  29     constant SPR_LR     : spr_num_t := 8;
  30     constant SPR_CTR    : spr_num_t := 9;
  31     constant SPR_TAR    : spr_num_t := 815;
  32     constant SPR_DSISR  : spr_num_t := 18;
  33     constant SPR_DAR    : spr_num_t := 19;
  34     constant SPR_TB     : spr_num_t := 268;
  35     constant SPR_TBU    : spr_num_t := 269;
  36     constant SPR_DEC    : spr_num_t := 22;
  37     constant SPR_SRR0   : spr_num_t := 26;
  38     constant SPR_SRR1   : spr_num_t := 27;
  39     constant SPR_CFAR   : spr_num_t := 28;
  40     constant SPR_HSRR0  : spr_num_t := 314;
  41     constant SPR_HSRR1  : spr_num_t := 315;
  42     constant SPR_SPRG0  : spr_num_t := 272;
  43     constant SPR_SPRG1  : spr_num_t := 273;
  44     constant SPR_SPRG2  : spr_num_t := 274;
  45     constant SPR_SPRG3  : spr_num_t := 275;
  46     constant SPR_SPRG3U : spr_num_t := 259;
  47     constant SPR_HSPRG0 : spr_num_t := 304;
  48     constant SPR_HSPRG1 : spr_num_t := 305;
  49     constant SPR_PID    : spr_num_t := 48;
  50     constant SPR_PRTBL  : spr_num_t := 720;
  51     constant SPR_PVR    : spr_num_t := 287;
  52
  53     -- GPR indices in the register file (GPR only)
  54     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  55
  56     -- Extended GPR indice (can hold an SPR)
  57     subtype gspr_index_t is std_ulogic_vector(5 downto 0);
  58
  59     -- Some SPRs are stored in the register file, they use the magic
  60     -- GPR numbers above 31.
  61     --
  62     -- The function fast_spr_num() returns the corresponding fast
  63     -- pseudo-GPR number for a given SPR number. The result MSB
  64     -- indicates if this is indeed a fast SPR. If clear, then
  65     -- the SPR is not stored in the GPR file.
  66     --
  67     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
  68
  69     -- Indices conversion functions
  70     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
  71     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
  72     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
  73     function is_fast_spr(s: gspr_index_t) return std_ulogic;
  74
  75     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
  76     -- in the CR file as a kind of CR extension (with a separate write
  77     -- control). The rest is stored as a fast SPR.
  78     type xer_common_t is record
  79         ca : std_ulogic;
  80         ca32 : std_ulogic;
  81         ov : std_ulogic;
  82         ov32 : std_ulogic;
  83         so : std_ulogic;
  84     end record;
  85     constant xerc_init : xer_common_t := (others => '0');
  86
  87     type irq_state_t is (WRITE_SRR0, WRITE_SRR1);
  88
  89     -- For now, fixed 16 sources, make this either a parametric
  90     -- package of some sort or an unconstrainted array.
  91     type ics_to_icp_t is record
  92         -- Level interrupts only, ICS just keeps prsenting the
  93         -- highest priority interrupt. Once handling edge, something
  94         -- smarter involving handshake & reject support will be needed
  95         src : std_ulogic_vector(3 downto 0);
  96         pri : std_ulogic_vector(7 downto 0);
  97     end record;
  98
  99     -- This needs to die...
 100     type ctrl_t is record
 101         tb: std_ulogic_vector(63 downto 0);
 102         dec: std_ulogic_vector(63 downto 0);
 103         msr: std_ulogic_vector(63 downto 0);
 104         cfar: std_ulogic_vector(63 downto 0);
 105         irq_state : irq_state_t;
 106         srr1: std_ulogic_vector(63 downto 0);
 107     end record;
 108
 109     type Fetch1ToIcacheType is record
 110         req: std_ulogic;
 111         virt_mode : std_ulogic;
 112         priv_mode : std_ulogic;
 113         big_endian : std_ulogic;
 114         stop_mark: std_ulogic;
 115         sequential: std_ulogic;
 116         nia: std_ulogic_vector(63 downto 0);
 117     end record;
 118
 119     type IcacheToDecode1Type is record
 120         valid: std_ulogic;
 121         stop_mark: std_ulogic;
 122         fetch_failed: std_ulogic;
 123         nia: std_ulogic_vector(63 downto 0);
 124         insn: std_ulogic_vector(31 downto 0);
 125     end record;
 126
 127     type Decode1ToDecode2Type is record
 128         valid: std_ulogic;
 129         stop_mark : std_ulogic;
 130         nia: std_ulogic_vector(63 downto 0);
 131         insn: std_ulogic_vector(31 downto 0);
 132         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
 133         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
 134         decode: decode_rom_t;
 135         br_pred: std_ulogic; -- Branch was predicted to be taken
 136     end record;
 137     constant Decode1ToDecode2Init : Decode1ToDecode2Type :=
 138         (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'),
 139          ispr1 => (others => '0'), ispr2 => (others => '0'), decode => decode_rom_init, br_pred => '0');
 140
 141     type Decode1ToFetch1Type is record
 142         redirect     : std_ulogic;
 143         redirect_nia : std_ulogic_vector(63 downto 0);
 144     end record;
 145
 146     type Decode2ToExecute1Type is record
 147         valid: std_ulogic;
 148         unit : unit_t;
 149         insn_type: insn_type_t;
 150         nia: std_ulogic_vector(63 downto 0);
 151         write_reg: gspr_index_t;
 152         read_reg1: gspr_index_t;
 153         read_reg2: gspr_index_t;
 154         read_data1: std_ulogic_vector(63 downto 0);
 155         read_data2: std_ulogic_vector(63 downto 0);
 156         read_data3: std_ulogic_vector(63 downto 0);
 157         bypass_data1: std_ulogic;
 158         bypass_data2: std_ulogic;
 159         bypass_data3: std_ulogic;
 160         cr: std_ulogic_vector(31 downto 0);
 161         bypass_cr : std_ulogic;
 162         xerc: xer_common_t;
 163         lr: std_ulogic;
 164         rc: std_ulogic;
 165         oe: std_ulogic;
 166         invert_a: std_ulogic;
 167         invert_out: std_ulogic;
 168         input_carry: carry_in_t;
 169         output_carry: std_ulogic;
 170         input_cr: std_ulogic;
 171         output_cr: std_ulogic;
 172         is_32bit: std_ulogic;
 173         is_signed: std_ulogic;
 174         insn: std_ulogic_vector(31 downto 0);
 175         data_len: std_ulogic_vector(3 downto 0);
 176         byte_reverse : std_ulogic;
 177         sign_extend : std_ulogic;                       -- do we need to sign extend?
 178         update : std_ulogic;                            -- is this an update instruction?
 179         reserve : std_ulogic;                           -- set for larx/stcx
 180         br_pred : std_ulogic;
 181     end record;
 182     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 183         (valid => '0', unit => NONE, insn_type => OP_ILLEGAL, bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
 184          bypass_cr => '0', lr => '0', rc => '0', oe => '0', invert_a => '0',
 185          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
 186          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0', br_pred => '0',
 187          byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'), read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'), cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'), others => (others => '0'));
 188
 189     type MultiplyInputType is record
 190         valid: std_ulogic;
 191         data1: std_ulogic_vector(63 downto 0);
 192         data2: std_ulogic_vector(63 downto 0);
 193         addend: std_ulogic_vector(127 downto 0);
 194         is_32bit: std_ulogic;
 195         not_result: std_ulogic;
 196     end record;
 197     constant MultiplyInputInit : MultiplyInputType := (valid => '0',
 198                                                        is_32bit => '0', not_result => '0',
 199                                                        others => (others => '0'));
 200
 201     type MultiplyOutputType is record
 202         valid: std_ulogic;
 203         result: std_ulogic_vector(127 downto 0);
 204         overflow : std_ulogic;
 205     end record;
 206     constant MultiplyOutputInit : MultiplyOutputType := (valid => '0', overflow => '0',
 207                                                          others => (others => '0'));
 208
 209     type Execute1ToDividerType is record
 210         valid: std_ulogic;
 211         dividend: std_ulogic_vector(63 downto 0);
 212         divisor: std_ulogic_vector(63 downto 0);
 213         is_signed: std_ulogic;
 214         is_32bit: std_ulogic;
 215         is_extended: std_ulogic;
 216         is_modulus: std_ulogic;
 217         neg_result: std_ulogic;
 218     end record;
 219     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 220                                                               is_extended => '0', is_modulus => '0',
 221                                                               neg_result => '0', others => (others => '0'));
 222
 223     type Decode2ToRegisterFileType is record
 224         read1_enable : std_ulogic;
 225         read1_reg : gspr_index_t;
 226         read2_enable : std_ulogic;
 227         read2_reg : gspr_index_t;
 228         read3_enable : std_ulogic;
 229         read3_reg : gpr_index_t;
 230     end record;
 231
 232     type RegisterFileToDecode2Type is record
 233         read1_data : std_ulogic_vector(63 downto 0);
 234         read2_data : std_ulogic_vector(63 downto 0);
 235         read3_data : std_ulogic_vector(63 downto 0);
 236     end record;
 237
 238     type Decode2ToCrFileType is record
 239         read : std_ulogic;
 240     end record;
 241
 242     type CrFileToDecode2Type is record
 243         read_cr_data   : std_ulogic_vector(31 downto 0);
 244         read_xerc_data : xer_common_t;
 245     end record;
 246
 247     type Execute1ToFetch1Type is record
 248         redirect: std_ulogic;
 249         virt_mode: std_ulogic;
 250         priv_mode: std_ulogic;
 251         big_endian: std_ulogic;
 252         mode_32bit: std_ulogic;
 253         redirect_nia: std_ulogic_vector(63 downto 0);
 254     end record;
 255     constant Execute1ToFetch1Init : Execute1ToFetch1Type := (redirect => '0', virt_mode => '0',
 256                                                              priv_mode => '0', big_endian => '0',
 257                                                              mode_32bit => '0', others => (others => '0'));
 258
 259     type Execute1ToLoadstore1Type is record
 260         valid : std_ulogic;
 261         op : insn_type_t;                               -- what ld/st or m[tf]spr or TLB op to do
 262         nia : std_ulogic_vector(63 downto 0);
 263         insn : std_ulogic_vector(31 downto 0);
 264         addr1 : std_ulogic_vector(63 downto 0);
 265         addr2 : std_ulogic_vector(63 downto 0);
 266         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 267         write_reg : gpr_index_t;
 268         length : std_ulogic_vector(3 downto 0);
 269         ci : std_ulogic;                                -- cache-inhibited load/store
 270         byte_reverse : std_ulogic;
 271         sign_extend : std_ulogic;                       -- do we need to sign extend?
 272         update : std_ulogic;                            -- is this an update instruction?
 273         update_reg : gpr_index_t;                       -- if so, the register to update
 274         xerc : xer_common_t;
 275         reserve : std_ulogic;                           -- set for larx/stcx.
 276         rc : std_ulogic;                                -- set for stcx.
 277         virt_mode : std_ulogic;                         -- do translation through TLB
 278         priv_mode : std_ulogic;                         -- privileged mode (MSR[PR] = 0)
 279         mode_32bit : std_ulogic;                        -- trim addresses to 32 bits
 280     end record;
 281     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
 282                                                                      sign_extend => '0', update => '0', xerc => xerc_init,
 283                                                                      reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
 284                                                                      nia => (others => '0'), insn => (others => '0'),
 285                                                                      addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'), length => (others => '0'),
 286                                                                      mode_32bit => '0', others => (others => '0'));
 287
 288     type Loadstore1ToExecute1Type is record
 289         busy : std_ulogic;
 290         exception : std_ulogic;
 291         alignment : std_ulogic;
 292         invalid : std_ulogic;
 293         perm_error : std_ulogic;
 294         rc_error : std_ulogic;
 295         badtree : std_ulogic;
 296         segment_fault : std_ulogic;
 297         instr_fault : std_ulogic;
 298     end record;
 299
 300     type Loadstore1ToDcacheType is record
 301         valid : std_ulogic;
 302         load : std_ulogic;                              -- is this a load
 303         dcbz : std_ulogic;
 304         nc : std_ulogic;
 305         reserve : std_ulogic;
 306         virt_mode : std_ulogic;
 307         priv_mode : std_ulogic;
 308         addr : std_ulogic_vector(63 downto 0);
 309         data : std_ulogic_vector(63 downto 0);
 310         byte_sel : std_ulogic_vector(7 downto 0);
 311     end record;
 312
 313     type DcacheToLoadstore1Type is record
 314         valid : std_ulogic;
 315         data : std_ulogic_vector(63 downto 0);
 316         store_done : std_ulogic;
 317         error : std_ulogic;
 318         cache_paradox : std_ulogic;
 319     end record;
 320
 321     type Loadstore1ToMmuType is record
 322         valid : std_ulogic;
 323         tlbie : std_ulogic;
 324         slbia : std_ulogic;
 325         mtspr : std_ulogic;
 326         iside : std_ulogic;
 327         load  : std_ulogic;
 328         priv  : std_ulogic;
 329         sprn  : std_ulogic_vector(9 downto 0);
 330         addr  : std_ulogic_vector(63 downto 0);
 331         rs    : std_ulogic_vector(63 downto 0);
 332     end record;
 333
 334     type MmuToLoadstore1Type is record
 335         done       : std_ulogic;
 336         err        : std_ulogic;
 337         invalid    : std_ulogic;
 338         badtree    : std_ulogic;
 339         segerr     : std_ulogic;
 340         perm_error : std_ulogic;
 341         rc_error   : std_ulogic;
 342         sprval     : std_ulogic_vector(63 downto 0);
 343     end record;
 344
 345     type MmuToDcacheType is record
 346         valid : std_ulogic;
 347         tlbie : std_ulogic;
 348         doall : std_ulogic;
 349         tlbld : std_ulogic;
 350         addr  : std_ulogic_vector(63 downto 0);
 351         pte   : std_ulogic_vector(63 downto 0);
 352     end record;
 353
 354     type DcacheToMmuType is record
 355         stall : std_ulogic;
 356         done  : std_ulogic;
 357         err   : std_ulogic;
 358         data  : std_ulogic_vector(63 downto 0);
 359     end record;
 360
 361     type MmuToIcacheType is record
 362         tlbld : std_ulogic;
 363         tlbie : std_ulogic;
 364         doall : std_ulogic;
 365         addr  : std_ulogic_vector(63 downto 0);
 366         pte   : std_ulogic_vector(63 downto 0);
 367     end record;
 368
 369     type Loadstore1ToWritebackType is record
 370         valid : std_ulogic;
 371         write_enable: std_ulogic;
 372         write_reg : gpr_index_t;
 373         write_data : std_ulogic_vector(63 downto 0);
 374         xerc : xer_common_t;
 375         rc : std_ulogic;
 376         store_done : std_ulogic;
 377     end record;
 378     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType := (valid => '0', write_enable => '0', xerc => xerc_init,
 379                                                                        rc => '0', store_done => '0', write_data => (others => '0'), others => (others => '0'));
 380
 381     type Execute1ToWritebackType is record
 382         valid: std_ulogic;
 383         rc : std_ulogic;
 384         mode_32bit : std_ulogic;
 385         write_enable : std_ulogic;
 386         write_reg: gspr_index_t;
 387         write_data: std_ulogic_vector(63 downto 0);
 388         write_cr_enable : std_ulogic;
 389         write_cr_mask : std_ulogic_vector(7 downto 0);
 390         write_cr_data : std_ulogic_vector(31 downto 0);
 391         write_xerc_enable : std_ulogic;
 392         xerc : xer_common_t;
 393         exc_write_enable : std_ulogic;
 394         exc_write_reg : gspr_index_t;
 395         exc_write_data : std_ulogic_vector(63 downto 0);
 396     end record;
 397     constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', mode_32bit => '0', write_enable => '0',
 398                                                                    write_cr_enable => '0', exc_write_enable => '0',
 399                                                                    write_xerc_enable => '0', xerc => xerc_init,
 400                                    write_data => (others => '0'), write_cr_mask => (others => '0'),
 401                                    write_cr_data => (others => '0'), write_reg => (others => '0'),
 402                                    exc_write_reg => (others => '0'), exc_write_data => (others => '0'));
 403
 404     type DividerToExecute1Type is record
 405         valid: std_ulogic;
 406         write_reg_data: std_ulogic_vector(63 downto 0);
 407         overflow : std_ulogic;
 408     end record;
 409     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 410                                                                others => (others => '0'));
 411
 412     type WritebackToRegisterFileType is record
 413         write_reg : gspr_index_t;
 414         write_data : std_ulogic_vector(63 downto 0);
 415         write_enable : std_ulogic;
 416     end record;
 417     constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
 418
 419     type WritebackToCrFileType is record
 420         write_cr_enable : std_ulogic;
 421         write_cr_mask : std_ulogic_vector(7 downto 0);
 422         write_cr_data : std_ulogic_vector(31 downto 0);
 423         write_xerc_enable : std_ulogic;
 424         write_xerc_data : xer_common_t;
 425     end record;
 426     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 427                                                                write_xerc_data => xerc_init,
 428                                                                write_cr_mask => (others => '0'),
 429                                                                write_cr_data => (others => '0'));
 430
 431 end common;
 432
 433 package body common is
 434     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 435     begin
 436         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 437     end;
 438     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 439        variable n : integer range 0 to 31;
 440        -- tmp variable introduced as workaround for VCS compilation
 441        -- simulation was failing with subtype constraint mismatch error
 442        -- see GitHub PR #173
 443        variable tmp : std_ulogic_vector(4 downto 0);
 444     begin
 445        case spr is
 446        when SPR_LR =>
 447            n := 0;
 448        when SPR_CTR =>
 449            n:= 1;
 450        when SPR_SRR0 =>
 451            n := 2;
 452        when SPR_SRR1 =>
 453            n := 3;
 454        when SPR_HSRR0 =>
 455            n := 4;
 456        when SPR_HSRR1 =>
 457            n := 5;
 458        when SPR_SPRG0 =>
 459            n := 6;
 460        when SPR_SPRG1 =>
 461            n := 7;
 462        when SPR_SPRG2 =>
 463            n := 8;
 464        when SPR_SPRG3 | SPR_SPRG3U =>
 465            n := 9;
 466        when SPR_HSPRG0 =>
 467            n := 10;
 468        when SPR_HSPRG1 =>
 469            n := 11;
 470        when SPR_XER =>
 471            n := 12;
 472        when SPR_TAR =>
 473            n := 13;
 474        when others =>
 475            n := 0;
 476            return "000000";
 477        end case;
 478        tmp := std_ulogic_vector(to_unsigned(n, 5));
 479        return "1" & tmp;
 480     end;
 481
 482     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 483     begin
 484         return i(4 downto 0);
 485     end;
 486
 487     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 488     begin
 489         return "0" & i;
 490     end;
 491
 492     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 493     begin
 494         if s(5) = '1' then
 495             return s;
 496         else
 497             return gpr_to_gspr(g);
 498         end if;
 499     end;
 500
 501     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 502     begin
 503         return s(5);
 504     end;
 505 end common;