common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7
   8 package common is
   9     -- Processor Version Number
  10     constant PVR_MICROWATT  : std_ulogic_vector(31 downto 0) := x"00630000";
  11
  12     -- MSR bit numbers
  13     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  14     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  15     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  16     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  17     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  18     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  19     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  20
  21     -- SPR numbers
  22     subtype spr_num_t is integer range 0 to 1023;
  23
  24     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  25
  26     constant SPR_XER    : spr_num_t := 1;
  27     constant SPR_LR     : spr_num_t := 8;
  28     constant SPR_CTR    : spr_num_t := 9;
  29     constant SPR_DSISR  : spr_num_t := 18;
  30     constant SPR_DAR    : spr_num_t := 19;
  31     constant SPR_TB     : spr_num_t := 268;
  32     constant SPR_TBU    : spr_num_t := 269;
  33     constant SPR_DEC    : spr_num_t := 22;
  34     constant SPR_SRR0   : spr_num_t := 26;
  35     constant SPR_SRR1   : spr_num_t := 27;
  36     constant SPR_CFAR   : spr_num_t := 28;
  37     constant SPR_HSRR0  : spr_num_t := 314;
  38     constant SPR_HSRR1  : spr_num_t := 315;
  39     constant SPR_SPRG0  : spr_num_t := 272;
  40     constant SPR_SPRG1  : spr_num_t := 273;
  41     constant SPR_SPRG2  : spr_num_t := 274;
  42     constant SPR_SPRG3  : spr_num_t := 275;
  43     constant SPR_SPRG3U : spr_num_t := 259;
  44     constant SPR_HSPRG0 : spr_num_t := 304;
  45     constant SPR_HSPRG1 : spr_num_t := 305;
  46     constant SPR_PID    : spr_num_t := 48;
  47     constant SPR_PRTBL  : spr_num_t := 720;
  48     constant SPR_PVR    : spr_num_t := 287;
  49
  50     -- GPR indices in the register file (GPR only)
  51     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  52
  53     -- Extended GPR indice (can hold an SPR)
  54     subtype gspr_index_t is std_ulogic_vector(5 downto 0);
  55
  56     -- Some SPRs are stored in the register file, they use the magic
  57     -- GPR numbers above 31.
  58     --
  59     -- The function fast_spr_num() returns the corresponding fast
  60     -- pseudo-GPR number for a given SPR number. The result MSB
  61     -- indicates if this is indeed a fast SPR. If clear, then
  62     -- the SPR is not stored in the GPR file.
  63     --
  64     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
  65
  66     -- Indices conversion functions
  67     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
  68     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
  69     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
  70     function is_fast_spr(s: gspr_index_t) return std_ulogic;
  71
  72     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
  73     -- in the CR file as a kind of CR extension (with a separate write
  74     -- control). The rest is stored as a fast SPR.
  75     type xer_common_t is record
  76         ca : std_ulogic;
  77         ca32 : std_ulogic;
  78         ov : std_ulogic;
  79         ov32 : std_ulogic;
  80         so : std_ulogic;
  81     end record;
  82     constant xerc_init : xer_common_t := (others => '0');
  83
  84     type irq_state_t is (WRITE_SRR0, WRITE_SRR1);
  85
  86     -- For now, fixed 16 sources, make this either a parametric
  87     -- package of some sort or an unconstrainted array.
  88     type ics_to_icp_t is record
  89         -- Level interrupts only, ICS just keeps prsenting the
  90         -- highest priority interrupt. Once handling edge, something
  91         -- smarter involving handshake & reject support will be needed
  92         src : std_ulogic_vector(3 downto 0);
  93         pri : std_ulogic_vector(7 downto 0);
  94     end record;
  95
  96     -- This needs to die...
  97     type ctrl_t is record
  98         tb: std_ulogic_vector(63 downto 0);
  99         dec: std_ulogic_vector(63 downto 0);
 100         msr: std_ulogic_vector(63 downto 0);
 101         cfar: std_ulogic_vector(63 downto 0);
 102         irq_state : irq_state_t;
 103         srr1: std_ulogic_vector(63 downto 0);
 104     end record;
 105
 106     type Fetch1ToIcacheType is record
 107         req: std_ulogic;
 108         virt_mode : std_ulogic;
 109         priv_mode : std_ulogic;
 110         stop_mark: std_ulogic;
 111         sequential: std_ulogic;
 112         nia: std_ulogic_vector(63 downto 0);
 113     end record;
 114
 115     type IcacheToDecode1Type is record
 116         valid: std_ulogic;
 117         stop_mark: std_ulogic;
 118         fetch_failed: std_ulogic;
 119         nia: std_ulogic_vector(63 downto 0);
 120         insn: std_ulogic_vector(31 downto 0);
 121     end record;
 122
 123     type Decode1ToDecode2Type is record
 124         valid: std_ulogic;
 125         stop_mark : std_ulogic;
 126         nia: std_ulogic_vector(63 downto 0);
 127         insn: std_ulogic_vector(31 downto 0);
 128         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
 129         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
 130         decode: decode_rom_t;
 131         br_pred: std_ulogic; -- Branch was predicted to be taken
 132     end record;
 133     constant Decode1ToDecode2Init : Decode1ToDecode2Type :=
 134         (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'),
 135          ispr1 => (others => '0'), ispr2 => (others => '0'), decode => decode_rom_init, br_pred => '0');
 136
 137     type Decode1ToFetch1Type is record
 138         redirect     : std_ulogic;
 139         redirect_nia : std_ulogic_vector(63 downto 0);
 140     end record;
 141
 142     type Decode2ToExecute1Type is record
 143         valid: std_ulogic;
 144         unit : unit_t;
 145         insn_type: insn_type_t;
 146         nia: std_ulogic_vector(63 downto 0);
 147         write_reg: gspr_index_t;
 148         read_reg1: gspr_index_t;
 149         read_reg2: gspr_index_t;
 150         read_data1: std_ulogic_vector(63 downto 0);
 151         read_data2: std_ulogic_vector(63 downto 0);
 152         read_data3: std_ulogic_vector(63 downto 0);
 153         bypass_data1: std_ulogic;
 154         bypass_data2: std_ulogic;
 155         bypass_data3: std_ulogic;
 156         cr: std_ulogic_vector(31 downto 0);
 157         bypass_cr : std_ulogic;
 158         xerc: xer_common_t;
 159         lr: std_ulogic;
 160         rc: std_ulogic;
 161         oe: std_ulogic;
 162         invert_a: std_ulogic;
 163         invert_out: std_ulogic;
 164         input_carry: carry_in_t;
 165         output_carry: std_ulogic;
 166         input_cr: std_ulogic;
 167         output_cr: std_ulogic;
 168         is_32bit: std_ulogic;
 169         is_signed: std_ulogic;
 170         insn: std_ulogic_vector(31 downto 0);
 171         data_len: std_ulogic_vector(3 downto 0);
 172         byte_reverse : std_ulogic;
 173         sign_extend : std_ulogic;                       -- do we need to sign extend?
 174         update : std_ulogic;                            -- is this an update instruction?
 175         reserve : std_ulogic;                           -- set for larx/stcx
 176         br_pred : std_ulogic;
 177     end record;
 178     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 179         (valid => '0', unit => NONE, insn_type => OP_ILLEGAL, bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
 180          bypass_cr => '0', lr => '0', rc => '0', oe => '0', invert_a => '0',
 181          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
 182          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0', br_pred => '0',
 183          byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'), read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'), cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'), others => (others => '0'));
 184
 185     type Execute1ToMultiplyType is record
 186         valid: std_ulogic;
 187         data1: std_ulogic_vector(63 downto 0);
 188         data2: std_ulogic_vector(63 downto 0);
 189         is_32bit: std_ulogic;
 190         neg_result: std_ulogic;
 191     end record;
 192     constant Execute1ToMultiplyInit : Execute1ToMultiplyType := (valid => '0',
 193                                                                  is_32bit => '0', neg_result => '0',
 194                                                                  others => (others => '0'));
 195
 196     type Execute1ToDividerType is record
 197         valid: std_ulogic;
 198         dividend: std_ulogic_vector(63 downto 0);
 199         divisor: std_ulogic_vector(63 downto 0);
 200         is_signed: std_ulogic;
 201         is_32bit: std_ulogic;
 202         is_extended: std_ulogic;
 203         is_modulus: std_ulogic;
 204         neg_result: std_ulogic;
 205     end record;
 206     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 207                                                               is_extended => '0', is_modulus => '0',
 208                                                               neg_result => '0', others => (others => '0'));
 209
 210     type Decode2ToRegisterFileType is record
 211         read1_enable : std_ulogic;
 212         read1_reg : gspr_index_t;
 213         read2_enable : std_ulogic;
 214         read2_reg : gspr_index_t;
 215         read3_enable : std_ulogic;
 216         read3_reg : gpr_index_t;
 217     end record;
 218
 219     type RegisterFileToDecode2Type is record
 220         read1_data : std_ulogic_vector(63 downto 0);
 221         read2_data : std_ulogic_vector(63 downto 0);
 222         read3_data : std_ulogic_vector(63 downto 0);
 223     end record;
 224
 225     type Decode2ToCrFileType is record
 226         read : std_ulogic;
 227     end record;
 228
 229     type CrFileToDecode2Type is record
 230         read_cr_data   : std_ulogic_vector(31 downto 0);
 231         read_xerc_data : xer_common_t;
 232     end record;
 233
 234     type Execute1ToFetch1Type is record
 235         redirect: std_ulogic;
 236         virt_mode: std_ulogic;
 237         priv_mode: std_ulogic;
 238         redirect_nia: std_ulogic_vector(63 downto 0);
 239     end record;
 240     constant Execute1ToFetch1Init : Execute1ToFetch1Type := (redirect => '0', virt_mode => '0',
 241                                                              priv_mode => '0', others => (others => '0'));
 242
 243     type Execute1ToLoadstore1Type is record
 244         valid : std_ulogic;
 245         op : insn_type_t;                               -- what ld/st or m[tf]spr or TLB op to do
 246         nia : std_ulogic_vector(63 downto 0);
 247         insn : std_ulogic_vector(31 downto 0);
 248         addr1 : std_ulogic_vector(63 downto 0);
 249         addr2 : std_ulogic_vector(63 downto 0);
 250         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 251         write_reg : gpr_index_t;
 252         length : std_ulogic_vector(3 downto 0);
 253         ci : std_ulogic;                                -- cache-inhibited load/store
 254         byte_reverse : std_ulogic;
 255         sign_extend : std_ulogic;                       -- do we need to sign extend?
 256         update : std_ulogic;                            -- is this an update instruction?
 257         update_reg : gpr_index_t;                       -- if so, the register to update
 258         xerc : xer_common_t;
 259         reserve : std_ulogic;                           -- set for larx/stcx.
 260         rc : std_ulogic;                                -- set for stcx.
 261         virt_mode : std_ulogic;                         -- do translation through TLB
 262         priv_mode : std_ulogic;                         -- privileged mode (MSR[PR] = 0)
 263     end record;
 264     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
 265                                                                      sign_extend => '0', update => '0', xerc => xerc_init,
 266                                                                      reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
 267                                                                      nia => (others => '0'), insn => (others => '0'),
 268                                                                      addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'), length => (others => '0'),
 269                                                                      others => (others => '0'));
 270
 271     type Loadstore1ToExecute1Type is record
 272         busy : std_ulogic;
 273         exception : std_ulogic;
 274         invalid : std_ulogic;
 275         perm_error : std_ulogic;
 276         rc_error : std_ulogic;
 277         badtree : std_ulogic;
 278         segment_fault : std_ulogic;
 279         instr_fault : std_ulogic;
 280     end record;
 281
 282     type Loadstore1ToDcacheType is record
 283         valid : std_ulogic;
 284         load : std_ulogic;                              -- is this a load
 285         dcbz : std_ulogic;
 286         nc : std_ulogic;
 287         reserve : std_ulogic;
 288         virt_mode : std_ulogic;
 289         priv_mode : std_ulogic;
 290         addr : std_ulogic_vector(63 downto 0);
 291         data : std_ulogic_vector(63 downto 0);
 292         byte_sel : std_ulogic_vector(7 downto 0);
 293     end record;
 294
 295     type DcacheToLoadstore1Type is record
 296         valid : std_ulogic;
 297         data : std_ulogic_vector(63 downto 0);
 298         store_done : std_ulogic;
 299         error : std_ulogic;
 300         cache_paradox : std_ulogic;
 301     end record;
 302
 303     type Loadstore1ToMmuType is record
 304         valid : std_ulogic;
 305         tlbie : std_ulogic;
 306         slbia : std_ulogic;
 307         mtspr : std_ulogic;
 308         iside : std_ulogic;
 309         load  : std_ulogic;
 310         priv  : std_ulogic;
 311         sprn  : std_ulogic_vector(9 downto 0);
 312         addr  : std_ulogic_vector(63 downto 0);
 313         rs    : std_ulogic_vector(63 downto 0);
 314     end record;
 315
 316     type MmuToLoadstore1Type is record
 317         done       : std_ulogic;
 318         invalid    : std_ulogic;
 319         badtree    : std_ulogic;
 320         segerr     : std_ulogic;
 321         perm_error : std_ulogic;
 322         rc_error   : std_ulogic;
 323         sprval     : std_ulogic_vector(63 downto 0);
 324     end record;
 325
 326     type MmuToDcacheType is record
 327         valid : std_ulogic;
 328         tlbie : std_ulogic;
 329         doall : std_ulogic;
 330         tlbld : std_ulogic;
 331         addr  : std_ulogic_vector(63 downto 0);
 332         pte   : std_ulogic_vector(63 downto 0);
 333     end record;
 334
 335     type DcacheToMmuType is record
 336         stall : std_ulogic;
 337         done  : std_ulogic;
 338         err   : std_ulogic;
 339         data  : std_ulogic_vector(63 downto 0);
 340     end record;
 341
 342     type MmuToIcacheType is record
 343         tlbld : std_ulogic;
 344         tlbie : std_ulogic;
 345         doall : std_ulogic;
 346         addr  : std_ulogic_vector(63 downto 0);
 347         pte   : std_ulogic_vector(63 downto 0);
 348     end record;
 349
 350     type Loadstore1ToWritebackType is record
 351         valid : std_ulogic;
 352         write_enable: std_ulogic;
 353         write_reg : gpr_index_t;
 354         write_data : std_ulogic_vector(63 downto 0);
 355         xerc : xer_common_t;
 356         rc : std_ulogic;
 357         store_done : std_ulogic;
 358     end record;
 359     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType := (valid => '0', write_enable => '0', xerc => xerc_init,
 360                                                                        rc => '0', store_done => '0', write_data => (others => '0'), others => (others => '0'));
 361
 362     type Execute1ToWritebackType is record
 363         valid: std_ulogic;
 364         rc : std_ulogic;
 365         write_enable : std_ulogic;
 366         write_reg: gspr_index_t;
 367         write_data: std_ulogic_vector(63 downto 0);
 368         write_cr_enable : std_ulogic;
 369         write_cr_mask : std_ulogic_vector(7 downto 0);
 370         write_cr_data : std_ulogic_vector(31 downto 0);
 371         write_xerc_enable : std_ulogic;
 372         xerc : xer_common_t;
 373         exc_write_enable : std_ulogic;
 374         exc_write_reg : gspr_index_t;
 375         exc_write_data : std_ulogic_vector(63 downto 0);
 376     end record;
 377     constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', write_enable => '0',
 378                                                                    write_cr_enable => '0', exc_write_enable => '0',
 379                                                                    write_xerc_enable => '0', xerc => xerc_init,
 380                                    write_data => (others => '0'), write_cr_mask => (others => '0'),
 381                                    write_cr_data => (others => '0'), write_reg => (others => '0'),
 382                                    exc_write_reg => (others => '0'), exc_write_data => (others => '0'));
 383
 384     type MultiplyToExecute1Type is record
 385         valid: std_ulogic;
 386         result: std_ulogic_vector(127 downto 0);
 387         overflow : std_ulogic;
 388     end record;
 389     constant MultiplyToExecute1Init : MultiplyToExecute1Type := (valid => '0', overflow => '0',
 390                                                                  others => (others => '0'));
 391
 392     type DividerToExecute1Type is record
 393         valid: std_ulogic;
 394         write_reg_data: std_ulogic_vector(63 downto 0);
 395         overflow : std_ulogic;
 396     end record;
 397     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 398                                                                others => (others => '0'));
 399
 400     type WritebackToRegisterFileType is record
 401         write_reg : gspr_index_t;
 402         write_data : std_ulogic_vector(63 downto 0);
 403         write_enable : std_ulogic;
 404     end record;
 405     constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
 406
 407     type WritebackToCrFileType is record
 408         write_cr_enable : std_ulogic;
 409         write_cr_mask : std_ulogic_vector(7 downto 0);
 410         write_cr_data : std_ulogic_vector(31 downto 0);
 411         write_xerc_enable : std_ulogic;
 412         write_xerc_data : xer_common_t;
 413     end record;
 414     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 415                                                                write_xerc_data => xerc_init,
 416                                                                write_cr_mask => (others => '0'),
 417                                                                write_cr_data => (others => '0'));
 418
 419 end common;
 420
 421 package body common is
 422     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 423     begin
 424         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 425     end;
 426     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 427        variable n : integer range 0 to 31;
 428        -- tmp variable introduced as workaround for VCS compilation
 429        -- simulation was failing with subtype constraint mismatch error
 430        -- see GitHub PR #173
 431        variable tmp : std_ulogic_vector(4 downto 0);
 432     begin
 433        case spr is
 434        when SPR_LR =>
 435            n := 0;
 436        when SPR_CTR =>
 437            n:= 1;
 438        when SPR_SRR0 =>
 439            n := 2;
 440        when SPR_SRR1 =>
 441            n := 3;
 442        when SPR_HSRR0 =>
 443            n := 4;
 444        when SPR_HSRR1 =>
 445            n := 5;
 446        when SPR_SPRG0 =>
 447            n := 6;
 448        when SPR_SPRG1 =>
 449            n := 7;
 450        when SPR_SPRG2 =>
 451            n := 8;
 452        when SPR_SPRG3 | SPR_SPRG3U =>
 453            n := 9;
 454        when SPR_HSPRG0 =>
 455            n := 10;
 456        when SPR_HSPRG1 =>
 457            n := 11;
 458        when SPR_XER =>
 459            n := 12;
 460        when others =>
 461            n := 0;
 462            return "000000";
 463        end case;
 464        tmp := std_ulogic_vector(to_unsigned(n, 5));
 465        return "1" & tmp;
 466     end;
 467
 468     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 469     begin
 470         return i(4 downto 0);
 471     end;
 472
 473     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 474     begin
 475         return "0" & i;
 476     end;
 477
 478     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 479     begin
 480         if s(5) = '1' then
 481             return s;
 482         else
 483             return gpr_to_gspr(g);
 484         end if;
 485     end;
 486
 487     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 488     begin
 489         return s(5);
 490     end;
 491 end common;