common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7
   8 package common is
   9
  10     -- MSR bit numbers
  11     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  12     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  13     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  14     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  15     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  16     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  17     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  18
  19     -- SPR numbers
  20     subtype spr_num_t is integer range 0 to 1023;
  21
  22     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  23
  24     constant SPR_XER    : spr_num_t := 1;
  25     constant SPR_LR     : spr_num_t := 8;
  26     constant SPR_CTR    : spr_num_t := 9;
  27     constant SPR_DSISR  : spr_num_t := 18;
  28     constant SPR_DAR    : spr_num_t := 19;
  29     constant SPR_TB     : spr_num_t := 268;
  30     constant SPR_DEC    : spr_num_t := 22;
  31     constant SPR_SRR0   : spr_num_t := 26;
  32     constant SPR_SRR1   : spr_num_t := 27;
  33     constant SPR_HSRR0  : spr_num_t := 314;
  34     constant SPR_HSRR1  : spr_num_t := 315;
  35     constant SPR_SPRG0  : spr_num_t := 272;
  36     constant SPR_SPRG1  : spr_num_t := 273;
  37     constant SPR_SPRG2  : spr_num_t := 274;
  38     constant SPR_SPRG3  : spr_num_t := 275;
  39     constant SPR_SPRG3U : spr_num_t := 259;
  40     constant SPR_HSPRG0 : spr_num_t := 304;
  41     constant SPR_HSPRG1 : spr_num_t := 305;
  42     constant SPR_PGTBL0 : spr_num_t := 720;
  43
  44     -- GPR indices in the register file (GPR only)
  45     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  46
  47     -- Extended GPR indice (can hold an SPR)
  48     subtype gspr_index_t is std_ulogic_vector(5 downto 0);
  49
  50     -- Some SPRs are stored in the register file, they use the magic
  51     -- GPR numbers above 31.
  52     --
  53     -- The function fast_spr_num() returns the corresponding fast
  54     -- pseudo-GPR number for a given SPR number. The result MSB
  55     -- indicates if this is indeed a fast SPR. If clear, then
  56     -- the SPR is not stored in the GPR file.
  57     --
  58     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
  59
  60     -- Indices conversion functions
  61     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
  62     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
  63     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
  64     function is_fast_spr(s: gspr_index_t) return std_ulogic;
  65
  66     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
  67     -- in the CR file as a kind of CR extension (with a separate write
  68     -- control). The rest is stored as a fast SPR.
  69     type xer_common_t is record
  70         ca : std_ulogic;
  71         ca32 : std_ulogic;
  72         ov : std_ulogic;
  73         ov32 : std_ulogic;
  74         so : std_ulogic;
  75     end record;
  76     constant xerc_init : xer_common_t := (others => '0');
  77
  78     type irq_state_t is (WRITE_SRR0, WRITE_SRR1);
  79
  80     -- This needs to die...
  81     type ctrl_t is record
  82         tb: std_ulogic_vector(63 downto 0);
  83         dec: std_ulogic_vector(63 downto 0);
  84         msr: std_ulogic_vector(63 downto 0);
  85         irq_state : irq_state_t;
  86         irq_nia: std_ulogic_vector(63 downto 0);
  87         srr1: std_ulogic_vector(63 downto 0);
  88     end record;
  89
  90     type Fetch1ToIcacheType is record
  91         req: std_ulogic;
  92         stop_mark: std_ulogic;
  93         nia: std_ulogic_vector(63 downto 0);
  94     end record;
  95
  96     type IcacheToFetch2Type is record
  97         valid: std_ulogic;
  98         stop_mark: std_ulogic;
  99         nia: std_ulogic_vector(63 downto 0);
 100         insn: std_ulogic_vector(31 downto 0);
 101     end record;
 102
 103     type Fetch2ToDecode1Type is record
 104         valid: std_ulogic;
 105         stop_mark : std_ulogic;
 106         nia: std_ulogic_vector(63 downto 0);
 107         insn: std_ulogic_vector(31 downto 0);
 108     end record;
 109     constant Fetch2ToDecode1Init : Fetch2ToDecode1Type := (valid => '0', stop_mark => '0', others => (others => '0'));
 110
 111     type Decode1ToDecode2Type is record
 112         valid: std_ulogic;
 113         stop_mark : std_ulogic;
 114         nia: std_ulogic_vector(63 downto 0);
 115         insn: std_ulogic_vector(31 downto 0);
 116         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
 117         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
 118         decode: decode_rom_t;
 119     end record;
 120     constant Decode1ToDecode2Init : Decode1ToDecode2Type := (valid => '0', stop_mark => '0', decode => decode_rom_init, others => (others => '0'));
 121
 122     type Decode2ToExecute1Type is record
 123         valid: std_ulogic;
 124         unit : unit_t;
 125         insn_type: insn_type_t;
 126         nia: std_ulogic_vector(63 downto 0);
 127         write_reg: gspr_index_t;
 128         read_reg1: gspr_index_t;
 129         read_reg2: gspr_index_t;
 130         read_data1: std_ulogic_vector(63 downto 0);
 131         read_data2: std_ulogic_vector(63 downto 0);
 132         read_data3: std_ulogic_vector(63 downto 0);
 133         bypass_data1: std_ulogic;
 134         bypass_data2: std_ulogic;
 135         bypass_data3: std_ulogic;
 136         cr: std_ulogic_vector(31 downto 0);
 137         xerc: xer_common_t;
 138         lr: std_ulogic;
 139         rc: std_ulogic;
 140         oe: std_ulogic;
 141         invert_a: std_ulogic;
 142         invert_out: std_ulogic;
 143         input_carry: carry_in_t;
 144         output_carry: std_ulogic;
 145         input_cr: std_ulogic;
 146         output_cr: std_ulogic;
 147         is_32bit: std_ulogic;
 148         is_signed: std_ulogic;
 149         insn: std_ulogic_vector(31 downto 0);
 150         data_len: std_ulogic_vector(3 downto 0);
 151         byte_reverse : std_ulogic;
 152         sign_extend : std_ulogic;                       -- do we need to sign extend?
 153         update : std_ulogic;                            -- is this an update instruction?
 154         reserve : std_ulogic;                           -- set for larx/stcx
 155     end record;
 156     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 157         (valid => '0', unit => NONE, insn_type => OP_ILLEGAL, bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
 158          lr => '0', rc => '0', oe => '0', invert_a => '0',
 159          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
 160          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0',
 161          byte_reverse => '0', sign_extend => '0', update => '0', others => (others => '0'));
 162
 163     type Execute1ToMultiplyType is record
 164         valid: std_ulogic;
 165         insn_type: insn_type_t;
 166         data1: std_ulogic_vector(64 downto 0);
 167         data2: std_ulogic_vector(64 downto 0);
 168         is_32bit: std_ulogic;
 169     end record;
 170     constant Execute1ToMultiplyInit : Execute1ToMultiplyType := (valid => '0', insn_type => OP_ILLEGAL,
 171                                                                  is_32bit => '0',
 172                                                                  others => (others => '0'));
 173
 174     type Execute1ToDividerType is record
 175         valid: std_ulogic;
 176         dividend: std_ulogic_vector(63 downto 0);
 177         divisor: std_ulogic_vector(63 downto 0);
 178         is_signed: std_ulogic;
 179         is_32bit: std_ulogic;
 180         is_extended: std_ulogic;
 181         is_modulus: std_ulogic;
 182         neg_result: std_ulogic;
 183     end record;
 184     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 185                                                               is_extended => '0', is_modulus => '0',
 186                                                               neg_result => '0', others => (others => '0'));
 187
 188     type Decode2ToRegisterFileType is record
 189         read1_enable : std_ulogic;
 190         read1_reg : gspr_index_t;
 191         read2_enable : std_ulogic;
 192         read2_reg : gspr_index_t;
 193         read3_enable : std_ulogic;
 194         read3_reg : gpr_index_t;
 195     end record;
 196
 197     type RegisterFileToDecode2Type is record
 198         read1_data : std_ulogic_vector(63 downto 0);
 199         read2_data : std_ulogic_vector(63 downto 0);
 200         read3_data : std_ulogic_vector(63 downto 0);
 201     end record;
 202
 203     type Decode2ToCrFileType is record
 204         read : std_ulogic;
 205     end record;
 206
 207     type CrFileToDecode2Type is record
 208         read_cr_data   : std_ulogic_vector(31 downto 0);
 209         read_xerc_data : xer_common_t;
 210     end record;
 211
 212     type Execute1ToFetch1Type is record
 213         redirect: std_ulogic;
 214         redirect_nia: std_ulogic_vector(63 downto 0);
 215     end record;
 216     constant Execute1ToFetch1TypeInit : Execute1ToFetch1Type := (redirect => '0', others => (others => '0'));
 217
 218     type Execute1ToLoadstore1Type is record
 219         valid : std_ulogic;
 220         op : insn_type_t;                               -- what ld/st or m[tf]spr or TLB op to do
 221         addr1 : std_ulogic_vector(63 downto 0);
 222         addr2 : std_ulogic_vector(63 downto 0);
 223         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 224         write_reg : gpr_index_t;
 225         length : std_ulogic_vector(3 downto 0);
 226         ci : std_ulogic;                                -- cache-inhibited load/store
 227         byte_reverse : std_ulogic;
 228         sign_extend : std_ulogic;                       -- do we need to sign extend?
 229         update : std_ulogic;                            -- is this an update instruction?
 230         update_reg : gpr_index_t;                       -- if so, the register to update
 231         xerc : xer_common_t;
 232         reserve : std_ulogic;                           -- set for larx/stcx.
 233         rc : std_ulogic;                                -- set for stcx.
 234         virt_mode : std_ulogic;                         -- do translation through TLB
 235         priv_mode : std_ulogic;                         -- privileged mode (MSR[PR] = 0)
 236         spr_num : spr_num_t;                            -- SPR number for mfspr/mtspr
 237     end record;
 238     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
 239                                                                      sign_extend => '0', update => '0', xerc => xerc_init,
 240                                                                      reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
 241                                                                      spr_num => 0, others => (others => '0'));
 242
 243     type Loadstore1ToExecute1Type is record
 244         exception : std_ulogic;
 245         segment_fault : std_ulogic;
 246     end record;
 247
 248     type Loadstore1ToDcacheType is record
 249         valid : std_ulogic;
 250         load : std_ulogic;                              -- is this a load
 251         dcbz : std_ulogic;
 252         nc : std_ulogic;
 253         reserve : std_ulogic;
 254         virt_mode : std_ulogic;
 255         priv_mode : std_ulogic;
 256         addr : std_ulogic_vector(63 downto 0);
 257         data : std_ulogic_vector(63 downto 0);
 258         byte_sel : std_ulogic_vector(7 downto 0);
 259     end record;
 260
 261     type DcacheToLoadstore1Type is record
 262         valid : std_ulogic;
 263         data : std_ulogic_vector(63 downto 0);
 264         store_done : std_ulogic;
 265         error : std_ulogic;
 266         cache_paradox : std_ulogic;
 267     end record;
 268
 269     type Loadstore1ToMmuType is record
 270         valid : std_ulogic;
 271         tlbie : std_ulogic;
 272         mtspr : std_ulogic;
 273         load  : std_ulogic;
 274         priv  : std_ulogic;
 275         sprn  : std_ulogic_vector(3 downto 0);
 276         addr  : std_ulogic_vector(63 downto 0);
 277         rs    : std_ulogic_vector(63 downto 0);
 278     end record;
 279
 280     type MmuToLoadstore1Type is record
 281         done       : std_ulogic;
 282         invalid    : std_ulogic;
 283         badtree    : std_ulogic;
 284         segerr     : std_ulogic;
 285         perm_error : std_ulogic;
 286         rc_error   : std_ulogic;
 287         sprval     : std_ulogic_vector(63 downto 0);
 288     end record;
 289
 290     type MmuToDcacheType is record
 291         valid : std_ulogic;
 292         tlbie : std_ulogic;
 293         tlbld : std_ulogic;
 294         addr  : std_ulogic_vector(63 downto 0);
 295         pte   : std_ulogic_vector(63 downto 0);
 296     end record;
 297
 298     type DcacheToMmuType is record
 299         stall : std_ulogic;
 300         done  : std_ulogic;
 301         err   : std_ulogic;
 302         data  : std_ulogic_vector(63 downto 0);
 303     end record;
 304
 305     type Loadstore1ToWritebackType is record
 306         valid : std_ulogic;
 307         write_enable: std_ulogic;
 308         write_reg : gpr_index_t;
 309         write_data : std_ulogic_vector(63 downto 0);
 310         xerc : xer_common_t;
 311         rc : std_ulogic;
 312         store_done : std_ulogic;
 313     end record;
 314     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType := (valid => '0', write_enable => '0', xerc => xerc_init,
 315                                                                        rc => '0', store_done => '0', others => (others => '0'));
 316
 317     type Execute1ToWritebackType is record
 318         valid: std_ulogic;
 319         rc : std_ulogic;
 320         write_enable : std_ulogic;
 321         write_reg: gspr_index_t;
 322         write_data: std_ulogic_vector(63 downto 0);
 323         write_cr_enable : std_ulogic;
 324         write_cr_mask : std_ulogic_vector(7 downto 0);
 325         write_cr_data : std_ulogic_vector(31 downto 0);
 326         write_xerc_enable : std_ulogic;
 327         xerc : xer_common_t;
 328         exc_write_enable : std_ulogic;
 329         exc_write_reg : gspr_index_t;
 330         exc_write_data : std_ulogic_vector(63 downto 0);
 331     end record;
 332     constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', write_enable => '0',
 333                                                                    write_cr_enable => '0', exc_write_enable => '0',
 334                                                                    write_xerc_enable => '0', xerc => xerc_init,
 335                                                                    others => (others => '0'));
 336
 337     type MultiplyToExecute1Type is record
 338         valid: std_ulogic;
 339         write_reg_data: std_ulogic_vector(63 downto 0);
 340         overflow : std_ulogic;
 341     end record;
 342     constant MultiplyToExecute1Init : MultiplyToExecute1Type := (valid => '0', overflow => '0',
 343                                                                  others => (others => '0'));
 344
 345     type DividerToExecute1Type is record
 346         valid: std_ulogic;
 347         write_reg_data: std_ulogic_vector(63 downto 0);
 348         overflow : std_ulogic;
 349     end record;
 350     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 351                                                                others => (others => '0'));
 352
 353     type WritebackToRegisterFileType is record
 354         write_reg : gspr_index_t;
 355         write_data : std_ulogic_vector(63 downto 0);
 356         write_enable : std_ulogic;
 357     end record;
 358     constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', others => (others => '0'));
 359
 360     type WritebackToCrFileType is record
 361         write_cr_enable : std_ulogic;
 362         write_cr_mask : std_ulogic_vector(7 downto 0);
 363         write_cr_data : std_ulogic_vector(31 downto 0);
 364         write_xerc_enable : std_ulogic;
 365         write_xerc_data : xer_common_t;
 366     end record;
 367     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 368                                                                write_xerc_data => xerc_init,
 369                                                                others => (others => '0'));
 370
 371     type XicsToExecute1Type is record
 372         irq : std_ulogic;
 373     end record;
 374
 375 end common;
 376
 377 package body common is
 378     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 379     begin
 380         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 381     end;
 382     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 383        variable n : integer range 0 to 31;
 384     begin
 385        case spr is
 386        when SPR_LR =>
 387            n := 0;
 388        when SPR_CTR =>
 389            n:= 1;
 390        when SPR_SRR0 =>
 391            n := 2;
 392        when SPR_SRR1 =>
 393            n := 3;
 394        when SPR_HSRR0 =>
 395            n := 4;
 396        when SPR_HSRR1 =>
 397            n := 5;
 398        when SPR_SPRG0 =>
 399            n := 6;
 400        when SPR_SPRG1 =>
 401            n := 7;
 402        when SPR_SPRG2 =>
 403            n := 8;
 404        when SPR_SPRG3 | SPR_SPRG3U =>
 405            n := 9;
 406        when SPR_HSPRG0 =>
 407            n := 10;
 408        when SPR_HSPRG1 =>
 409            n := 11;
 410        when SPR_XER =>
 411            n := 12;
 412        when others =>
 413            n := 0;
 414            return "000000";
 415        end case;
 416        return "1" & std_ulogic_vector(to_unsigned(n, 5));
 417     end;
 418
 419     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 420     begin
 421         return i(4 downto 0);
 422     end;
 423
 424     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 425     begin
 426         return "0" & i;
 427     end;
 428
 429     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 430     begin
 431         if s(5) = '1' then
 432             return s;
 433         else
 434             return gpr_to_gspr(g);
 435         end if;
 436     end;
 437
 438     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 439     begin
 440         return s(5);
 441     end;
 442 end common;