common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7
   8 package common is
   9
  10     -- SPR numbers
  11     subtype spr_num_t is integer range 0 to 1023;
  12
  13     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  14
  15     constant SPR_XER    : spr_num_t := 1;
  16     constant SPR_LR     : spr_num_t := 8;
  17     constant SPR_CTR    : spr_num_t := 9;
  18     constant SPR_TB     : spr_num_t := 268;
  19     constant SPR_DEC    : spr_num_t := 22;
  20     constant SPR_SRR0   : spr_num_t := 26;
  21     constant SPR_SRR1   : spr_num_t := 27;
  22     constant SPR_HSRR0  : spr_num_t := 314;
  23     constant SPR_HSRR1  : spr_num_t := 315;
  24     constant SPR_SPRG0  : spr_num_t := 272;
  25     constant SPR_SPRG1  : spr_num_t := 273;
  26     constant SPR_SPRG2  : spr_num_t := 274;
  27     constant SPR_SPRG3  : spr_num_t := 275;
  28     constant SPR_SPRG3U : spr_num_t := 259;
  29     constant SPR_HSPRG0 : spr_num_t := 304;
  30     constant SPR_HSPRG1 : spr_num_t := 305;
  31
  32     -- GPR indices in the register file (GPR only)
  33     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  34
  35     -- Extended GPR indice (can hold an SPR)
  36     subtype gspr_index_t is std_ulogic_vector(5 downto 0);
  37
  38     -- Some SPRs are stored in the register file, they use the magic
  39     -- GPR numbers above 31.
  40     --
  41     -- The function fast_spr_num() returns the corresponding fast
  42     -- pseudo-GPR number for a given SPR number. The result MSB
  43     -- indicates if this is indeed a fast SPR. If clear, then
  44     -- the SPR is not stored in the GPR file.
  45     --
  46     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
  47
  48     -- Indices conversion functions
  49     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
  50     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
  51     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
  52     function is_fast_spr(s: gspr_index_t) return std_ulogic;
  53
  54     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
  55     -- in the CR file as a kind of CR extension (with a separate write
  56     -- control). The rest is stored as a fast SPR.
  57     type xer_common_t is record
  58         ca : std_ulogic;
  59         ca32 : std_ulogic;
  60         ov : std_ulogic;
  61         ov32 : std_ulogic;
  62         so : std_ulogic;
  63     end record;
  64     constant xerc_init : xer_common_t := (others => '0');
  65
  66     type irq_state_t is (WRITE_SRR0, WRITE_SRR1);
  67
  68     -- This needs to die...
  69     type ctrl_t is record
  70         tb: std_ulogic_vector(63 downto 0);
  71         dec: std_ulogic_vector(63 downto 0);
  72         msr: std_ulogic_vector(63 downto 0);
  73         irq_state : irq_state_t;
  74         irq_nia: std_ulogic_vector(63 downto 0);
  75         srr1: std_ulogic_vector(63 downto 0);
  76     end record;
  77
  78     type Fetch1ToIcacheType is record
  79         req: std_ulogic;
  80         stop_mark: std_ulogic;
  81         nia: std_ulogic_vector(63 downto 0);
  82     end record;
  83
  84     type IcacheToFetch2Type is record
  85         valid: std_ulogic;
  86         stop_mark: std_ulogic;
  87         nia: std_ulogic_vector(63 downto 0);
  88         insn: std_ulogic_vector(31 downto 0);
  89     end record;
  90
  91     type Fetch2ToDecode1Type is record
  92         valid: std_ulogic;
  93         stop_mark : std_ulogic;
  94         nia: std_ulogic_vector(63 downto 0);
  95         insn: std_ulogic_vector(31 downto 0);
  96     end record;
  97     constant Fetch2ToDecode1Init : Fetch2ToDecode1Type := (valid => '0', stop_mark => '0', others => (others => '0'));
  98
  99     type Decode1ToDecode2Type is record
 100         valid: std_ulogic;
 101         stop_mark : std_ulogic;
 102         nia: std_ulogic_vector(63 downto 0);
 103         insn: std_ulogic_vector(31 downto 0);
 104         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
 105         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
 106         decode: decode_rom_t;
 107     end record;
 108     constant Decode1ToDecode2Init : Decode1ToDecode2Type := (valid => '0', stop_mark => '0', decode => decode_rom_init, others => (others => '0'));
 109
 110     type Decode2ToExecute1Type is record
 111         valid: std_ulogic;
 112         insn_type: insn_type_t;
 113         nia: std_ulogic_vector(63 downto 0);
 114         write_reg: gspr_index_t;
 115         read_reg1: gspr_index_t;
 116         read_reg2: gspr_index_t;
 117         read_data1: std_ulogic_vector(63 downto 0);
 118         read_data2: std_ulogic_vector(63 downto 0);
 119         read_data3: std_ulogic_vector(63 downto 0);
 120         bypass_data1: std_ulogic;
 121         bypass_data2: std_ulogic;
 122         bypass_data3: std_ulogic;
 123         cr: std_ulogic_vector(31 downto 0);
 124         xerc: xer_common_t;
 125         lr: std_ulogic;
 126         rc: std_ulogic;
 127         oe: std_ulogic;
 128         invert_a: std_ulogic;
 129         invert_out: std_ulogic;
 130         input_carry: carry_in_t;
 131         output_carry: std_ulogic;
 132         input_cr: std_ulogic;
 133         output_cr: std_ulogic;
 134         is_32bit: std_ulogic;
 135         is_signed: std_ulogic;
 136         insn: std_ulogic_vector(31 downto 0);
 137         data_len: std_ulogic_vector(3 downto 0);
 138         byte_reverse : std_ulogic;
 139         sign_extend : std_ulogic;                       -- do we need to sign extend?
 140         update : std_ulogic;                            -- is this an update instruction?
 141         reserve : std_ulogic;                           -- set for larx/stcx
 142     end record;
 143     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 144         (valid => '0', insn_type => OP_ILLEGAL, bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
 145          lr => '0', rc => '0', oe => '0', invert_a => '0',
 146          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
 147          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0',
 148          byte_reverse => '0', sign_extend => '0', update => '0', others => (others => '0'));
 149
 150     type Execute1ToMultiplyType is record
 151         valid: std_ulogic;
 152         insn_type: insn_type_t;
 153         data1: std_ulogic_vector(64 downto 0);
 154         data2: std_ulogic_vector(64 downto 0);
 155         is_32bit: std_ulogic;
 156     end record;
 157     constant Execute1ToMultiplyInit : Execute1ToMultiplyType := (valid => '0', insn_type => OP_ILLEGAL,
 158                                                                  is_32bit => '0',
 159                                                                  others => (others => '0'));
 160
 161     type Execute1ToDividerType is record
 162         valid: std_ulogic;
 163         dividend: std_ulogic_vector(63 downto 0);
 164         divisor: std_ulogic_vector(63 downto 0);
 165         is_signed: std_ulogic;
 166         is_32bit: std_ulogic;
 167         is_extended: std_ulogic;
 168         is_modulus: std_ulogic;
 169         neg_result: std_ulogic;
 170     end record;
 171     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 172                                                               is_extended => '0', is_modulus => '0',
 173                                                               neg_result => '0', others => (others => '0'));
 174
 175     type Decode2ToRegisterFileType is record
 176         read1_enable : std_ulogic;
 177         read1_reg : gspr_index_t;
 178         read2_enable : std_ulogic;
 179         read2_reg : gspr_index_t;
 180         read3_enable : std_ulogic;
 181         read3_reg : gpr_index_t;
 182     end record;
 183
 184     type RegisterFileToDecode2Type is record
 185         read1_data : std_ulogic_vector(63 downto 0);
 186         read2_data : std_ulogic_vector(63 downto 0);
 187         read3_data : std_ulogic_vector(63 downto 0);
 188     end record;
 189
 190     type Decode2ToCrFileType is record
 191         read : std_ulogic;
 192     end record;
 193
 194     type CrFileToDecode2Type is record
 195         read_cr_data   : std_ulogic_vector(31 downto 0);
 196         read_xerc_data : xer_common_t;
 197     end record;
 198
 199     type Execute1ToFetch1Type is record
 200         redirect: std_ulogic;
 201         redirect_nia: std_ulogic_vector(63 downto 0);
 202     end record;
 203     constant Execute1ToFetch1TypeInit : Execute1ToFetch1Type := (redirect => '0', others => (others => '0'));
 204
 205     type Execute1ToLoadstore1Type is record
 206         valid : std_ulogic;
 207         load : std_ulogic;                              -- is this a load or store
 208         addr1 : std_ulogic_vector(63 downto 0);
 209         addr2 : std_ulogic_vector(63 downto 0);
 210         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 211         write_reg : gpr_index_t;
 212         length : std_ulogic_vector(3 downto 0);
 213         ci : std_ulogic;                                -- cache-inhibited load/store
 214         byte_reverse : std_ulogic;
 215         sign_extend : std_ulogic;                       -- do we need to sign extend?
 216         update : std_ulogic;                            -- is this an update instruction?
 217         update_reg : gpr_index_t;                       -- if so, the register to update
 218         xerc : xer_common_t;
 219         reserve : std_ulogic;                           -- set for larx/stcx.
 220         rc : std_ulogic;                                -- set for stcx.
 221     end record;
 222     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', load => '0', ci => '0', byte_reverse => '0',
 223                                                                      sign_extend => '0', update => '0', xerc => xerc_init,
 224                                                                      reserve => '0', rc => '0', others => (others => '0'));
 225
 226     type Loadstore1ToDcacheType is record
 227         valid : std_ulogic;
 228         load : std_ulogic;
 229         nc : std_ulogic;
 230         reserve : std_ulogic;
 231         addr : std_ulogic_vector(63 downto 0);
 232         data : std_ulogic_vector(63 downto 0);
 233         byte_sel : std_ulogic_vector(7 downto 0);
 234     end record;
 235
 236     type DcacheToLoadstore1Type is record
 237         valid : std_ulogic;
 238         data : std_ulogic_vector(63 downto 0);
 239         store_done : std_ulogic;
 240         error : std_ulogic;
 241     end record;
 242
 243     type Loadstore1ToWritebackType is record
 244         valid : std_ulogic;
 245         write_enable: std_ulogic;
 246         write_reg : gpr_index_t;
 247         write_data : std_ulogic_vector(63 downto 0);
 248         xerc : xer_common_t;
 249         rc : std_ulogic;
 250         store_done : std_ulogic;
 251     end record;
 252     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType := (valid => '0', write_enable => '0', xerc => xerc_init,
 253                                                                        rc => '0', store_done => '0', others => (others => '0'));
 254
 255     type Execute1ToWritebackType is record
 256         valid: std_ulogic;
 257         rc : std_ulogic;
 258         write_enable : std_ulogic;
 259         write_reg: gspr_index_t;
 260         write_data: std_ulogic_vector(63 downto 0);
 261         write_cr_enable : std_ulogic;
 262         write_cr_mask : std_ulogic_vector(7 downto 0);
 263         write_cr_data : std_ulogic_vector(31 downto 0);
 264         write_xerc_enable : std_ulogic;
 265         xerc : xer_common_t;
 266         exc_write_enable : std_ulogic;
 267         exc_write_reg : gspr_index_t;
 268         exc_write_data : std_ulogic_vector(63 downto 0);
 269     end record;
 270     constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', write_enable => '0',
 271                                                                    write_cr_enable => '0', exc_write_enable => '0',
 272                                                                    write_xerc_enable => '0', xerc => xerc_init,
 273                                                                    others => (others => '0'));
 274
 275     type MultiplyToExecute1Type is record
 276         valid: std_ulogic;
 277         write_reg_data: std_ulogic_vector(63 downto 0);
 278         overflow : std_ulogic;
 279     end record;
 280     constant MultiplyToExecute1Init : MultiplyToExecute1Type := (valid => '0', overflow => '0',
 281                                                                  others => (others => '0'));
 282
 283     type DividerToExecute1Type is record
 284         valid: std_ulogic;
 285         write_reg_data: std_ulogic_vector(63 downto 0);
 286         overflow : std_ulogic;
 287     end record;
 288     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 289                                                                others => (others => '0'));
 290
 291     type WritebackToRegisterFileType is record
 292         write_reg : gspr_index_t;
 293         write_data : std_ulogic_vector(63 downto 0);
 294         write_enable : std_ulogic;
 295     end record;
 296     constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', others => (others => '0'));
 297
 298     type WritebackToCrFileType is record
 299         write_cr_enable : std_ulogic;
 300         write_cr_mask : std_ulogic_vector(7 downto 0);
 301         write_cr_data : std_ulogic_vector(31 downto 0);
 302         write_xerc_enable : std_ulogic;
 303         write_xerc_data : xer_common_t;
 304     end record;
 305     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 306                                                                write_xerc_data => xerc_init,
 307                                                                others => (others => '0'));
 308
 309     type XicsToExecute1Type is record
 310         irq : std_ulogic;
 311     end record;
 312
 313 end common;
 314
 315 package body common is
 316     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 317     begin
 318         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 319     end;
 320     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 321        variable n : integer range 0 to 31;
 322     begin
 323        case spr is
 324        when SPR_LR =>
 325            n := 0;
 326        when SPR_CTR =>
 327            n:= 1;
 328        when SPR_SRR0 =>
 329            n := 2;
 330        when SPR_SRR1 =>
 331            n := 3;
 332        when SPR_HSRR0 =>
 333            n := 4;
 334        when SPR_HSRR1 =>
 335            n := 5;
 336        when SPR_SPRG0 =>
 337            n := 6;
 338        when SPR_SPRG1 =>
 339            n := 7;
 340        when SPR_SPRG2 =>
 341            n := 8;
 342        when SPR_SPRG3 | SPR_SPRG3U =>
 343            n := 9;
 344        when SPR_HSPRG0 =>
 345            n := 10;
 346        when SPR_HSPRG1 =>
 347            n := 11;
 348        when SPR_XER =>
 349            n := 12;
 350        when others =>
 351            n := 0;
 352            return "000000";
 353        end case;
 354        return "1" & std_ulogic_vector(to_unsigned(n, 5));
 355     end;
 356
 357     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 358     begin
 359         return i(4 downto 0);
 360     end;
 361
 362     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 363     begin
 364         return "0" & i;
 365     end;
 366
 367     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 368     begin
 369         if s(5) = '1' then
 370             return s;
 371         else
 372             return gpr_to_gspr(g);
 373         end if;
 374     end;
 375
 376     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 377     begin
 378         return s(5);
 379     end;
 380 end common;