common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7
   8 package common is
   9
  10     -- MSR bit numbers
  11     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  12     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  13     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  14     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  15     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  16     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  17     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  18
  19     -- SPR numbers
  20     subtype spr_num_t is integer range 0 to 1023;
  21
  22     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  23
  24     constant SPR_XER    : spr_num_t := 1;
  25     constant SPR_LR     : spr_num_t := 8;
  26     constant SPR_CTR    : spr_num_t := 9;
  27     constant SPR_DSISR  : spr_num_t := 18;
  28     constant SPR_DAR    : spr_num_t := 19;
  29     constant SPR_TB     : spr_num_t := 268;
  30     constant SPR_TBU    : spr_num_t := 269;
  31     constant SPR_DEC    : spr_num_t := 22;
  32     constant SPR_SRR0   : spr_num_t := 26;
  33     constant SPR_SRR1   : spr_num_t := 27;
  34     constant SPR_HSRR0  : spr_num_t := 314;
  35     constant SPR_HSRR1  : spr_num_t := 315;
  36     constant SPR_SPRG0  : spr_num_t := 272;
  37     constant SPR_SPRG1  : spr_num_t := 273;
  38     constant SPR_SPRG2  : spr_num_t := 274;
  39     constant SPR_SPRG3  : spr_num_t := 275;
  40     constant SPR_SPRG3U : spr_num_t := 259;
  41     constant SPR_HSPRG0 : spr_num_t := 304;
  42     constant SPR_HSPRG1 : spr_num_t := 305;
  43     constant SPR_PID    : spr_num_t := 48;
  44     constant SPR_PRTBL  : spr_num_t := 720;
  45
  46     -- GPR indices in the register file (GPR only)
  47     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  48
  49     -- Extended GPR indice (can hold an SPR)
  50     subtype gspr_index_t is std_ulogic_vector(5 downto 0);
  51
  52     -- Some SPRs are stored in the register file, they use the magic
  53     -- GPR numbers above 31.
  54     --
  55     -- The function fast_spr_num() returns the corresponding fast
  56     -- pseudo-GPR number for a given SPR number. The result MSB
  57     -- indicates if this is indeed a fast SPR. If clear, then
  58     -- the SPR is not stored in the GPR file.
  59     --
  60     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
  61
  62     -- Indices conversion functions
  63     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
  64     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
  65     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
  66     function is_fast_spr(s: gspr_index_t) return std_ulogic;
  67
  68     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
  69     -- in the CR file as a kind of CR extension (with a separate write
  70     -- control). The rest is stored as a fast SPR.
  71     type xer_common_t is record
  72         ca : std_ulogic;
  73         ca32 : std_ulogic;
  74         ov : std_ulogic;
  75         ov32 : std_ulogic;
  76         so : std_ulogic;
  77     end record;
  78     constant xerc_init : xer_common_t := (others => '0');
  79
  80     type irq_state_t is (WRITE_SRR0, WRITE_SRR1);
  81
  82     -- For now, fixed 16 sources, make this either a parametric
  83     -- package of some sort or an unconstrainted array.
  84     type ics_to_icp_t is record
  85         -- Level interrupts only, ICS just keeps prsenting the
  86         -- highest priority interrupt. Once handling edge, something
  87         -- smarter involving handshake & reject support will be needed
  88         src : std_ulogic_vector(3 downto 0);
  89         pri : std_ulogic_vector(7 downto 0);
  90     end record;
  91
  92     -- This needs to die...
  93     type ctrl_t is record
  94         tb: std_ulogic_vector(63 downto 0);
  95         dec: std_ulogic_vector(63 downto 0);
  96         msr: std_ulogic_vector(63 downto 0);
  97         irq_state : irq_state_t;
  98         irq_nia: std_ulogic_vector(63 downto 0);
  99         srr1: std_ulogic_vector(63 downto 0);
 100     end record;
 101
 102     type Fetch1ToIcacheType is record
 103         req: std_ulogic;
 104         virt_mode : std_ulogic;
 105         priv_mode : std_ulogic;
 106         stop_mark: std_ulogic;
 107         sequential: std_ulogic;
 108         nia: std_ulogic_vector(63 downto 0);
 109     end record;
 110
 111     type IcacheToDecode1Type is record
 112         valid: std_ulogic;
 113         stop_mark: std_ulogic;
 114         fetch_failed: std_ulogic;
 115         nia: std_ulogic_vector(63 downto 0);
 116         insn: std_ulogic_vector(31 downto 0);
 117     end record;
 118
 119     type Decode1ToDecode2Type is record
 120         valid: std_ulogic;
 121         stop_mark : std_ulogic;
 122         nia: std_ulogic_vector(63 downto 0);
 123         insn: std_ulogic_vector(31 downto 0);
 124         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
 125         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
 126         decode: decode_rom_t;
 127         br_pred: std_ulogic; -- Branch was predicted to be taken
 128     end record;
 129     constant Decode1ToDecode2Init : Decode1ToDecode2Type :=
 130         (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'),
 131          ispr1 => (others => '0'), ispr2 => (others => '0'), decode => decode_rom_init, br_pred => '0');
 132
 133     type Decode1ToFetch1Type is record
 134         redirect     : std_ulogic;
 135         redirect_nia : std_ulogic_vector(63 downto 0);
 136     end record;
 137
 138     type Decode2ToExecute1Type is record
 139         valid: std_ulogic;
 140         unit : unit_t;
 141         insn_type: insn_type_t;
 142         nia: std_ulogic_vector(63 downto 0);
 143         write_reg: gspr_index_t;
 144         read_reg1: gspr_index_t;
 145         read_reg2: gspr_index_t;
 146         read_data1: std_ulogic_vector(63 downto 0);
 147         read_data2: std_ulogic_vector(63 downto 0);
 148         read_data3: std_ulogic_vector(63 downto 0);
 149         bypass_data1: std_ulogic;
 150         bypass_data2: std_ulogic;
 151         bypass_data3: std_ulogic;
 152         cr: std_ulogic_vector(31 downto 0);
 153         xerc: xer_common_t;
 154         lr: std_ulogic;
 155         rc: std_ulogic;
 156         oe: std_ulogic;
 157         invert_a: std_ulogic;
 158         invert_out: std_ulogic;
 159         input_carry: carry_in_t;
 160         output_carry: std_ulogic;
 161         input_cr: std_ulogic;
 162         output_cr: std_ulogic;
 163         is_32bit: std_ulogic;
 164         is_signed: std_ulogic;
 165         insn: std_ulogic_vector(31 downto 0);
 166         data_len: std_ulogic_vector(3 downto 0);
 167         byte_reverse : std_ulogic;
 168         sign_extend : std_ulogic;                       -- do we need to sign extend?
 169         update : std_ulogic;                            -- is this an update instruction?
 170         reserve : std_ulogic;                           -- set for larx/stcx
 171         br_pred : std_ulogic;
 172     end record;
 173     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 174         (valid => '0', unit => NONE, insn_type => OP_ILLEGAL, bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
 175          lr => '0', rc => '0', oe => '0', invert_a => '0',
 176          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
 177          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0', br_pred => '0',
 178          byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'), read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'), cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'), others => (others => '0'));
 179
 180     type Execute1ToMultiplyType is record
 181         valid: std_ulogic;
 182         data1: std_ulogic_vector(63 downto 0);
 183         data2: std_ulogic_vector(63 downto 0);
 184         is_32bit: std_ulogic;
 185         neg_result: std_ulogic;
 186     end record;
 187     constant Execute1ToMultiplyInit : Execute1ToMultiplyType := (valid => '0',
 188                                                                  is_32bit => '0', neg_result => '0',
 189                                                                  others => (others => '0'));
 190
 191     type Execute1ToDividerType is record
 192         valid: std_ulogic;
 193         dividend: std_ulogic_vector(63 downto 0);
 194         divisor: std_ulogic_vector(63 downto 0);
 195         is_signed: std_ulogic;
 196         is_32bit: std_ulogic;
 197         is_extended: std_ulogic;
 198         is_modulus: std_ulogic;
 199         neg_result: std_ulogic;
 200     end record;
 201     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 202                                                               is_extended => '0', is_modulus => '0',
 203                                                               neg_result => '0', others => (others => '0'));
 204
 205     type Decode2ToRegisterFileType is record
 206         read1_enable : std_ulogic;
 207         read1_reg : gspr_index_t;
 208         read2_enable : std_ulogic;
 209         read2_reg : gspr_index_t;
 210         read3_enable : std_ulogic;
 211         read3_reg : gpr_index_t;
 212     end record;
 213
 214     type RegisterFileToDecode2Type is record
 215         read1_data : std_ulogic_vector(63 downto 0);
 216         read2_data : std_ulogic_vector(63 downto 0);
 217         read3_data : std_ulogic_vector(63 downto 0);
 218     end record;
 219
 220     type Decode2ToCrFileType is record
 221         read : std_ulogic;
 222     end record;
 223
 224     type CrFileToDecode2Type is record
 225         read_cr_data   : std_ulogic_vector(31 downto 0);
 226         read_xerc_data : xer_common_t;
 227     end record;
 228
 229     type Execute1ToFetch1Type is record
 230         redirect: std_ulogic;
 231         virt_mode: std_ulogic;
 232         priv_mode: std_ulogic;
 233         redirect_nia: std_ulogic_vector(63 downto 0);
 234     end record;
 235     constant Execute1ToFetch1TypeInit : Execute1ToFetch1Type := (redirect => '0', virt_mode => '0',
 236                                                                  priv_mode => '0', others => (others => '0'));
 237
 238     type Execute1ToLoadstore1Type is record
 239         valid : std_ulogic;
 240         op : insn_type_t;                               -- what ld/st or m[tf]spr or TLB op to do
 241         nia : std_ulogic_vector(63 downto 0);
 242         insn : std_ulogic_vector(31 downto 0);
 243         addr1 : std_ulogic_vector(63 downto 0);
 244         addr2 : std_ulogic_vector(63 downto 0);
 245         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 246         write_reg : gpr_index_t;
 247         length : std_ulogic_vector(3 downto 0);
 248         ci : std_ulogic;                                -- cache-inhibited load/store
 249         byte_reverse : std_ulogic;
 250         sign_extend : std_ulogic;                       -- do we need to sign extend?
 251         update : std_ulogic;                            -- is this an update instruction?
 252         update_reg : gpr_index_t;                       -- if so, the register to update
 253         xerc : xer_common_t;
 254         reserve : std_ulogic;                           -- set for larx/stcx.
 255         rc : std_ulogic;                                -- set for stcx.
 256         virt_mode : std_ulogic;                         -- do translation through TLB
 257         priv_mode : std_ulogic;                         -- privileged mode (MSR[PR] = 0)
 258     end record;
 259     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
 260                                                                      sign_extend => '0', update => '0', xerc => xerc_init,
 261                                                                      reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
 262                                                                      nia => (others => '0'), insn => (others => '0'),
 263                                                                      addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'), length => (others => '0'),
 264                                                                      others => (others => '0'));
 265
 266     type Loadstore1ToExecute1Type is record
 267         busy : std_ulogic;
 268         exception : std_ulogic;
 269         invalid : std_ulogic;
 270         perm_error : std_ulogic;
 271         rc_error : std_ulogic;
 272         badtree : std_ulogic;
 273         segment_fault : std_ulogic;
 274         instr_fault : std_ulogic;
 275     end record;
 276
 277     type Loadstore1ToDcacheType is record
 278         valid : std_ulogic;
 279         load : std_ulogic;                              -- is this a load
 280         dcbz : std_ulogic;
 281         nc : std_ulogic;
 282         reserve : std_ulogic;
 283         virt_mode : std_ulogic;
 284         priv_mode : std_ulogic;
 285         addr : std_ulogic_vector(63 downto 0);
 286         data : std_ulogic_vector(63 downto 0);
 287         byte_sel : std_ulogic_vector(7 downto 0);
 288     end record;
 289
 290     type DcacheToLoadstore1Type is record
 291         valid : std_ulogic;
 292         data : std_ulogic_vector(63 downto 0);
 293         store_done : std_ulogic;
 294         error : std_ulogic;
 295         cache_paradox : std_ulogic;
 296     end record;
 297
 298     type Loadstore1ToMmuType is record
 299         valid : std_ulogic;
 300         tlbie : std_ulogic;
 301         slbia : std_ulogic;
 302         mtspr : std_ulogic;
 303         iside : std_ulogic;
 304         load  : std_ulogic;
 305         priv  : std_ulogic;
 306         sprn  : std_ulogic_vector(9 downto 0);
 307         addr  : std_ulogic_vector(63 downto 0);
 308         rs    : std_ulogic_vector(63 downto 0);
 309     end record;
 310
 311     type MmuToLoadstore1Type is record
 312         done       : std_ulogic;
 313         invalid    : std_ulogic;
 314         badtree    : std_ulogic;
 315         segerr     : std_ulogic;
 316         perm_error : std_ulogic;
 317         rc_error   : std_ulogic;
 318         sprval     : std_ulogic_vector(63 downto 0);
 319     end record;
 320
 321     type MmuToDcacheType is record
 322         valid : std_ulogic;
 323         tlbie : std_ulogic;
 324         doall : std_ulogic;
 325         tlbld : std_ulogic;
 326         addr  : std_ulogic_vector(63 downto 0);
 327         pte   : std_ulogic_vector(63 downto 0);
 328     end record;
 329
 330     type DcacheToMmuType is record
 331         stall : std_ulogic;
 332         done  : std_ulogic;
 333         err   : std_ulogic;
 334         data  : std_ulogic_vector(63 downto 0);
 335     end record;
 336
 337     type MmuToIcacheType is record
 338         tlbld : std_ulogic;
 339         tlbie : std_ulogic;
 340         doall : std_ulogic;
 341         addr  : std_ulogic_vector(63 downto 0);
 342         pte   : std_ulogic_vector(63 downto 0);
 343     end record;
 344
 345     type Loadstore1ToWritebackType is record
 346         valid : std_ulogic;
 347         write_enable: std_ulogic;
 348         write_reg : gpr_index_t;
 349         write_data : std_ulogic_vector(63 downto 0);
 350         xerc : xer_common_t;
 351         rc : std_ulogic;
 352         store_done : std_ulogic;
 353     end record;
 354     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType := (valid => '0', write_enable => '0', xerc => xerc_init,
 355                                                                        rc => '0', store_done => '0', write_data => (others => '0'), others => (others => '0'));
 356
 357     type Execute1ToWritebackType is record
 358         valid: std_ulogic;
 359         rc : std_ulogic;
 360         write_enable : std_ulogic;
 361         write_reg: gspr_index_t;
 362         write_data: std_ulogic_vector(63 downto 0);
 363         write_cr_enable : std_ulogic;
 364         write_cr_mask : std_ulogic_vector(7 downto 0);
 365         write_cr_data : std_ulogic_vector(31 downto 0);
 366         write_xerc_enable : std_ulogic;
 367         xerc : xer_common_t;
 368         exc_write_enable : std_ulogic;
 369         exc_write_reg : gspr_index_t;
 370         exc_write_data : std_ulogic_vector(63 downto 0);
 371     end record;
 372     constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', write_enable => '0',
 373                                                                    write_cr_enable => '0', exc_write_enable => '0',
 374                                                                    write_xerc_enable => '0', xerc => xerc_init,
 375                                    write_data => (others => '0'), write_cr_mask => (others => '0'),
 376                                    write_cr_data => (others => '0'), write_reg => (others => '0'),
 377                                    exc_write_reg => (others => '0'), exc_write_data => (others => '0'));
 378
 379     type MultiplyToExecute1Type is record
 380         valid: std_ulogic;
 381         result: std_ulogic_vector(127 downto 0);
 382         overflow : std_ulogic;
 383     end record;
 384     constant MultiplyToExecute1Init : MultiplyToExecute1Type := (valid => '0', overflow => '0',
 385                                                                  others => (others => '0'));
 386
 387     type DividerToExecute1Type is record
 388         valid: std_ulogic;
 389         write_reg_data: std_ulogic_vector(63 downto 0);
 390         overflow : std_ulogic;
 391     end record;
 392     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 393                                                                others => (others => '0'));
 394
 395     type WritebackToRegisterFileType is record
 396         write_reg : gspr_index_t;
 397         write_data : std_ulogic_vector(63 downto 0);
 398         write_enable : std_ulogic;
 399     end record;
 400     constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
 401
 402     type WritebackToCrFileType is record
 403         write_cr_enable : std_ulogic;
 404         write_cr_mask : std_ulogic_vector(7 downto 0);
 405         write_cr_data : std_ulogic_vector(31 downto 0);
 406         write_xerc_enable : std_ulogic;
 407         write_xerc_data : xer_common_t;
 408     end record;
 409     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 410                                                                write_xerc_data => xerc_init,
 411                                                                write_cr_mask => (others => '0'),
 412                                                                write_cr_data => (others => '0'));
 413
 414 end common;
 415
 416 package body common is
 417     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 418     begin
 419         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 420     end;
 421     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 422        variable n : integer range 0 to 31;
 423        -- tmp variable introduced as workaround for VCS compilation
 424        -- simulation was failing with subtype constraint mismatch error
 425        -- see GitHub PR #173
 426        variable tmp : std_ulogic_vector(4 downto 0);
 427     begin
 428        case spr is
 429        when SPR_LR =>
 430            n := 0;
 431        when SPR_CTR =>
 432            n:= 1;
 433        when SPR_SRR0 =>
 434            n := 2;
 435        when SPR_SRR1 =>
 436            n := 3;
 437        when SPR_HSRR0 =>
 438            n := 4;
 439        when SPR_HSRR1 =>
 440            n := 5;
 441        when SPR_SPRG0 =>
 442            n := 6;
 443        when SPR_SPRG1 =>
 444            n := 7;
 445        when SPR_SPRG2 =>
 446            n := 8;
 447        when SPR_SPRG3 | SPR_SPRG3U =>
 448            n := 9;
 449        when SPR_HSPRG0 =>
 450            n := 10;
 451        when SPR_HSPRG1 =>
 452            n := 11;
 453        when SPR_XER =>
 454            n := 12;
 455        when others =>
 456            n := 0;
 457            return "000000";
 458        end case;
 459        tmp := std_ulogic_vector(to_unsigned(n, 5));
 460        return "1" & tmp;
 461     end;
 462
 463     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 464     begin
 465         return i(4 downto 0);
 466     end;
 467
 468     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 469     begin
 470         return "0" & i;
 471     end;
 472
 473     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 474     begin
 475         if s(5) = '1' then
 476             return s;
 477         else
 478             return gpr_to_gspr(g);
 479         end if;
 480     end;
 481
 482     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 483     begin
 484         return s(5);
 485     end;
 486 end common;