common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7
   8 package common is
   9
  10     -- SPR numbers
  11     subtype spr_num_t is integer range 0 to 1023;
  12
  13     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  14
  15     constant SPR_XER    : spr_num_t := 1;
  16     constant SPR_LR     : spr_num_t := 8;
  17     constant SPR_CTR    : spr_num_t := 9;
  18     constant SPR_TB     : spr_num_t := 268;
  19     constant SPR_SRR0   : spr_num_t := 26;
  20     constant SPR_SRR1   : spr_num_t := 27;
  21     constant SPR_HSRR0  : spr_num_t := 314;
  22     constant SPR_HSRR1  : spr_num_t := 315;
  23     constant SPR_SPRG0  : spr_num_t := 272;
  24     constant SPR_SPRG1  : spr_num_t := 273;
  25     constant SPR_SPRG2  : spr_num_t := 274;
  26     constant SPR_SPRG3  : spr_num_t := 275;
  27     constant SPR_SPRG3U : spr_num_t := 259;
  28     constant SPR_HSPRG0 : spr_num_t := 304;
  29     constant SPR_HSPRG1 : spr_num_t := 305;
  30
  31     -- GPR indices in the register file (GPR only)
  32     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  33
  34     -- Extended GPR indice (can hold an SPR)
  35     subtype gspr_index_t is std_ulogic_vector(5 downto 0);
  36
  37     -- Some SPRs are stored in the register file, they use the magic
  38     -- GPR numbers above 31.
  39     --
  40     -- The function fast_spr_num() returns the corresponding fast
  41     -- pseudo-GPR number for a given SPR number. The result MSB
  42     -- indicates if this is indeed a fast SPR. If clear, then
  43     -- the SPR is not stored in the GPR file.
  44     --
  45     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
  46
  47     -- Indices conversion functions
  48     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
  49     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
  50     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
  51     function is_fast_spr(s: gspr_index_t) return std_ulogic;
  52
  53     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
  54     -- in the CR file as a kind of CR extension (with a separate write
  55     -- control). The rest is stored as a fast SPR.
  56     type xer_common_t is record
  57         ca : std_ulogic;
  58         ca32 : std_ulogic;
  59         ov : std_ulogic;
  60         ov32 : std_ulogic;
  61         so : std_ulogic;
  62     end record;
  63     constant xerc_init : xer_common_t := (others => '0');
  64
  65     -- This needs to die...
  66     type ctrl_t is record
  67         tb: std_ulogic_vector(63 downto 0);
  68     end record;
  69
  70     type Fetch1ToIcacheType is record
  71         req: std_ulogic;
  72         stop_mark: std_ulogic;
  73         nia: std_ulogic_vector(63 downto 0);
  74     end record;
  75
  76     type IcacheToFetch2Type is record
  77         valid: std_ulogic;
  78         stop_mark: std_ulogic;
  79         nia: std_ulogic_vector(63 downto 0);
  80         insn: std_ulogic_vector(31 downto 0);
  81     end record;
  82
  83     type Fetch2ToDecode1Type is record
  84         valid: std_ulogic;
  85         stop_mark : std_ulogic;
  86         nia: std_ulogic_vector(63 downto 0);
  87         insn: std_ulogic_vector(31 downto 0);
  88     end record;
  89     constant Fetch2ToDecode1Init : Fetch2ToDecode1Type := (valid => '0', stop_mark => '0', others => (others => '0'));
  90
  91     type Decode1ToDecode2Type is record
  92         valid: std_ulogic;
  93         stop_mark : std_ulogic;
  94         nia: std_ulogic_vector(63 downto 0);
  95         insn: std_ulogic_vector(31 downto 0);
  96         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
  97         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
  98         decode: decode_rom_t;
  99     end record;
 100     constant Decode1ToDecode2Init : Decode1ToDecode2Type := (valid => '0', stop_mark => '0', decode => decode_rom_init, others => (others => '0'));
 101
 102     type Decode2ToExecute1Type is record
 103         valid: std_ulogic;
 104         insn_type: insn_type_t;
 105         nia: std_ulogic_vector(63 downto 0);
 106         write_reg: gspr_index_t;
 107         read_reg1: gspr_index_t;
 108         read_reg2: gspr_index_t;
 109         read_data1: std_ulogic_vector(63 downto 0);
 110         read_data2: std_ulogic_vector(63 downto 0);
 111         read_data3: std_ulogic_vector(63 downto 0);
 112         bypass_data1: std_ulogic;
 113         bypass_data2: std_ulogic;
 114         bypass_data3: std_ulogic;
 115         cr: std_ulogic_vector(31 downto 0);
 116         xerc: xer_common_t;
 117         lr: std_ulogic;
 118         rc: std_ulogic;
 119         oe: std_ulogic;
 120         invert_a: std_ulogic;
 121         invert_out: std_ulogic;
 122         input_carry: carry_in_t;
 123         output_carry: std_ulogic;
 124         input_cr: std_ulogic;
 125         output_cr: std_ulogic;
 126         is_32bit: std_ulogic;
 127         is_signed: std_ulogic;
 128         insn: std_ulogic_vector(31 downto 0);
 129         data_len: std_ulogic_vector(3 downto 0);
 130         byte_reverse : std_ulogic;
 131         sign_extend : std_ulogic;                       -- do we need to sign extend?
 132         update : std_ulogic;                            -- is this an update instruction?
 133         reserve : std_ulogic;                           -- set for larx/stcx
 134     end record;
 135     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 136         (valid => '0', insn_type => OP_ILLEGAL, bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
 137          lr => '0', rc => '0', oe => '0', invert_a => '0',
 138          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
 139          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0',
 140          byte_reverse => '0', sign_extend => '0', update => '0', others => (others => '0'));
 141
 142     type Execute1ToMultiplyType is record
 143         valid: std_ulogic;
 144         insn_type: insn_type_t;
 145         data1: std_ulogic_vector(64 downto 0);
 146         data2: std_ulogic_vector(64 downto 0);
 147         is_32bit: std_ulogic;
 148     end record;
 149     constant Execute1ToMultiplyInit : Execute1ToMultiplyType := (valid => '0', insn_type => OP_ILLEGAL,
 150                                                                  is_32bit => '0',
 151                                                                  others => (others => '0'));
 152
 153     type Execute1ToDividerType is record
 154         valid: std_ulogic;
 155         dividend: std_ulogic_vector(63 downto 0);
 156         divisor: std_ulogic_vector(63 downto 0);
 157         is_signed: std_ulogic;
 158         is_32bit: std_ulogic;
 159         is_extended: std_ulogic;
 160         is_modulus: std_ulogic;
 161         neg_result: std_ulogic;
 162     end record;
 163     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 164                                                               is_extended => '0', is_modulus => '0',
 165                                                               neg_result => '0', others => (others => '0'));
 166
 167     type Decode2ToRegisterFileType is record
 168         read1_enable : std_ulogic;
 169         read1_reg : gspr_index_t;
 170         read2_enable : std_ulogic;
 171         read2_reg : gspr_index_t;
 172         read3_enable : std_ulogic;
 173         read3_reg : gpr_index_t;
 174     end record;
 175
 176     type RegisterFileToDecode2Type is record
 177         read1_data : std_ulogic_vector(63 downto 0);
 178         read2_data : std_ulogic_vector(63 downto 0);
 179         read3_data : std_ulogic_vector(63 downto 0);
 180     end record;
 181
 182     type Decode2ToCrFileType is record
 183         read : std_ulogic;
 184     end record;
 185
 186     type CrFileToDecode2Type is record
 187         read_cr_data   : std_ulogic_vector(31 downto 0);
 188         read_xerc_data : xer_common_t;
 189     end record;
 190
 191     type Execute1ToFetch1Type is record
 192         redirect: std_ulogic;
 193         redirect_nia: std_ulogic_vector(63 downto 0);
 194     end record;
 195     constant Execute1ToFetch1TypeInit : Execute1ToFetch1Type := (redirect => '0', others => (others => '0'));
 196
 197     type Execute1ToLoadstore1Type is record
 198         valid : std_ulogic;
 199         load : std_ulogic;                              -- is this a load or store
 200         addr1 : std_ulogic_vector(63 downto 0);
 201         addr2 : std_ulogic_vector(63 downto 0);
 202         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 203         write_reg : gpr_index_t;
 204         length : std_ulogic_vector(3 downto 0);
 205         byte_reverse : std_ulogic;
 206         sign_extend : std_ulogic;                       -- do we need to sign extend?
 207         update : std_ulogic;                            -- is this an update instruction?
 208         update_reg : gpr_index_t;                       -- if so, the register to update
 209         xerc : xer_common_t;
 210         reserve : std_ulogic;                           -- set for larx/stcx.
 211         rc : std_ulogic;                                -- set for stcx.
 212     end record;
 213     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', load => '0', byte_reverse => '0',
 214                                                                      sign_extend => '0', update => '0', xerc => xerc_init,
 215                                                                      reserve => '0', rc => '0', others => (others => '0'));
 216
 217     type Loadstore1ToDcacheType is record
 218         valid : std_ulogic;
 219         load : std_ulogic;
 220         nc : std_ulogic;
 221         reserve : std_ulogic;
 222         addr : std_ulogic_vector(63 downto 0);
 223         data : std_ulogic_vector(63 downto 0);
 224         byte_sel : std_ulogic_vector(7 downto 0);
 225     end record;
 226
 227     type DcacheToLoadstore1Type is record
 228         valid : std_ulogic;
 229         data : std_ulogic_vector(63 downto 0);
 230         store_done : std_ulogic;
 231         error : std_ulogic;
 232     end record;
 233
 234     type Loadstore1ToWritebackType is record
 235         valid : std_ulogic;
 236         write_enable: std_ulogic;
 237         write_reg : gpr_index_t;
 238         write_data : std_ulogic_vector(63 downto 0);
 239         xerc : xer_common_t;
 240         rc : std_ulogic;
 241         store_done : std_ulogic;
 242     end record;
 243     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType := (valid => '0', write_enable => '0', xerc => xerc_init,
 244                                                                        rc => '0', store_done => '0', others => (others => '0'));
 245
 246     type Execute1ToWritebackType is record
 247         valid: std_ulogic;
 248         rc : std_ulogic;
 249         write_enable : std_ulogic;
 250         write_reg: gspr_index_t;
 251         write_data: std_ulogic_vector(63 downto 0);
 252         write_cr_enable : std_ulogic;
 253         write_cr_mask : std_ulogic_vector(7 downto 0);
 254         write_cr_data : std_ulogic_vector(31 downto 0);
 255         write_xerc_enable : std_ulogic;
 256         xerc : xer_common_t;
 257     end record;
 258     constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', write_enable => '0',
 259                                                                    write_cr_enable => '0',
 260                                                                    write_xerc_enable => '0', xerc => xerc_init,
 261                                                                    others => (others => '0'));
 262
 263     type MultiplyToExecute1Type is record
 264         valid: std_ulogic;
 265         write_reg_data: std_ulogic_vector(63 downto 0);
 266         overflow : std_ulogic;
 267     end record;
 268     constant MultiplyToExecute1Init : MultiplyToExecute1Type := (valid => '0', overflow => '0',
 269                                                                  others => (others => '0'));
 270
 271     type DividerToExecute1Type is record
 272         valid: std_ulogic;
 273         write_reg_data: std_ulogic_vector(63 downto 0);
 274         overflow : std_ulogic;
 275     end record;
 276     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 277                                                                others => (others => '0'));
 278
 279     type WritebackToRegisterFileType is record
 280         write_reg : gspr_index_t;
 281         write_data : std_ulogic_vector(63 downto 0);
 282         write_enable : std_ulogic;
 283     end record;
 284     constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', others => (others => '0'));
 285
 286     type WritebackToCrFileType is record
 287         write_cr_enable : std_ulogic;
 288         write_cr_mask : std_ulogic_vector(7 downto 0);
 289         write_cr_data : std_ulogic_vector(31 downto 0);
 290         write_xerc_enable : std_ulogic;
 291         write_xerc_data : xer_common_t;
 292     end record;
 293     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 294                                                                write_xerc_data => xerc_init,
 295                                                                others => (others => '0'));
 296 end common;
 297
 298 package body common is
 299     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 300     begin
 301         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 302     end;
 303     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 304        variable n : integer range 0 to 31;
 305     begin
 306        case spr is
 307        when SPR_LR =>
 308            n := 0;
 309        when SPR_CTR =>
 310            n:= 1;
 311        when SPR_SRR0 =>
 312            n := 2;
 313        when SPR_SRR1 =>
 314            n := 3;
 315        when SPR_HSRR0 =>
 316            n := 4;
 317        when SPR_HSRR1 =>
 318            n := 5;
 319        when SPR_SPRG0 =>
 320            n := 6;
 321        when SPR_SPRG1 =>
 322            n := 7;
 323        when SPR_SPRG2 =>
 324            n := 8;
 325        when SPR_SPRG3 | SPR_SPRG3U =>
 326            n := 9;
 327        when SPR_HSPRG0 =>
 328            n := 10;
 329        when SPR_HSPRG1 =>
 330            n := 11;
 331        when SPR_XER =>
 332            n := 12;
 333        when others =>
 334            n := 0;
 335            return "000000";
 336        end case;
 337        return "1" & std_ulogic_vector(to_unsigned(n, 5));
 338     end;
 339
 340     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 341     begin
 342         return i(4 downto 0);
 343     end;
 344
 345     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 346     begin
 347         return "0" & i;
 348     end;
 349
 350     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 351     begin
 352         if s(5) = '1' then
 353             return s;
 354         else
 355             return gpr_to_gspr(g);
 356         end if;
 357     end;
 358
 359     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 360     begin
 361         return s(5);
 362     end;
 363 end common;