common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7
   8 package common is
   9
  10     -- MSR bit numbers
  11     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  12     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  13     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  14     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  15     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  16     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  17     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  18
  19     -- SPR numbers
  20     subtype spr_num_t is integer range 0 to 1023;
  21
  22     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  23
  24     constant SPR_XER    : spr_num_t := 1;
  25     constant SPR_LR     : spr_num_t := 8;
  26     constant SPR_CTR    : spr_num_t := 9;
  27     constant SPR_DSISR  : spr_num_t := 18;
  28     constant SPR_DAR    : spr_num_t := 19;
  29     constant SPR_TB     : spr_num_t := 268;
  30     constant SPR_DEC    : spr_num_t := 22;
  31     constant SPR_SRR0   : spr_num_t := 26;
  32     constant SPR_SRR1   : spr_num_t := 27;
  33     constant SPR_HSRR0  : spr_num_t := 314;
  34     constant SPR_HSRR1  : spr_num_t := 315;
  35     constant SPR_SPRG0  : spr_num_t := 272;
  36     constant SPR_SPRG1  : spr_num_t := 273;
  37     constant SPR_SPRG2  : spr_num_t := 274;
  38     constant SPR_SPRG3  : spr_num_t := 275;
  39     constant SPR_SPRG3U : spr_num_t := 259;
  40     constant SPR_HSPRG0 : spr_num_t := 304;
  41     constant SPR_HSPRG1 : spr_num_t := 305;
  42     constant SPR_PID    : spr_num_t := 48;
  43     constant SPR_PRTBL  : spr_num_t := 720;
  44
  45     -- GPR indices in the register file (GPR only)
  46     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  47
  48     -- Extended GPR indice (can hold an SPR)
  49     subtype gspr_index_t is std_ulogic_vector(5 downto 0);
  50
  51     -- Some SPRs are stored in the register file, they use the magic
  52     -- GPR numbers above 31.
  53     --
  54     -- The function fast_spr_num() returns the corresponding fast
  55     -- pseudo-GPR number for a given SPR number. The result MSB
  56     -- indicates if this is indeed a fast SPR. If clear, then
  57     -- the SPR is not stored in the GPR file.
  58     --
  59     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
  60
  61     -- Indices conversion functions
  62     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
  63     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
  64     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
  65     function is_fast_spr(s: gspr_index_t) return std_ulogic;
  66
  67     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
  68     -- in the CR file as a kind of CR extension (with a separate write
  69     -- control). The rest is stored as a fast SPR.
  70     type xer_common_t is record
  71         ca : std_ulogic;
  72         ca32 : std_ulogic;
  73         ov : std_ulogic;
  74         ov32 : std_ulogic;
  75         so : std_ulogic;
  76     end record;
  77     constant xerc_init : xer_common_t := (others => '0');
  78
  79     type irq_state_t is (WRITE_SRR0, WRITE_SRR1);
  80
  81     -- This needs to die...
  82     type ctrl_t is record
  83         tb: std_ulogic_vector(63 downto 0);
  84         dec: std_ulogic_vector(63 downto 0);
  85         msr: std_ulogic_vector(63 downto 0);
  86         irq_state : irq_state_t;
  87         irq_nia: std_ulogic_vector(63 downto 0);
  88         srr1: std_ulogic_vector(63 downto 0);
  89     end record;
  90
  91     type Fetch1ToIcacheType is record
  92         req: std_ulogic;
  93         virt_mode : std_ulogic;
  94         priv_mode : std_ulogic;
  95         stop_mark: std_ulogic;
  96         sequential: std_ulogic;
  97         nia: std_ulogic_vector(63 downto 0);
  98     end record;
  99
 100     type IcacheToDecode1Type is record
 101         valid: std_ulogic;
 102         stop_mark: std_ulogic;
 103         fetch_failed: std_ulogic;
 104         nia: std_ulogic_vector(63 downto 0);
 105         insn: std_ulogic_vector(31 downto 0);
 106     end record;
 107
 108     type Decode1ToDecode2Type is record
 109         valid: std_ulogic;
 110         stop_mark : std_ulogic;
 111         nia: std_ulogic_vector(63 downto 0);
 112         insn: std_ulogic_vector(31 downto 0);
 113         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
 114         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
 115         decode: decode_rom_t;
 116     end record;
 117     constant Decode1ToDecode2Init : Decode1ToDecode2Type := (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'), ispr1 => (others => '0'), ispr2 => (others => '0'), decode => decode_rom_init);
 118
 119     type Decode2ToExecute1Type is record
 120         valid: std_ulogic;
 121         unit : unit_t;
 122         insn_type: insn_type_t;
 123         nia: std_ulogic_vector(63 downto 0);
 124         write_reg: gspr_index_t;
 125         read_reg1: gspr_index_t;
 126         read_reg2: gspr_index_t;
 127         read_data1: std_ulogic_vector(63 downto 0);
 128         read_data2: std_ulogic_vector(63 downto 0);
 129         read_data3: std_ulogic_vector(63 downto 0);
 130         bypass_data1: std_ulogic;
 131         bypass_data2: std_ulogic;
 132         bypass_data3: std_ulogic;
 133         cr: std_ulogic_vector(31 downto 0);
 134         xerc: xer_common_t;
 135         lr: std_ulogic;
 136         rc: std_ulogic;
 137         oe: std_ulogic;
 138         invert_a: std_ulogic;
 139         invert_out: std_ulogic;
 140         input_carry: carry_in_t;
 141         output_carry: std_ulogic;
 142         input_cr: std_ulogic;
 143         output_cr: std_ulogic;
 144         is_32bit: std_ulogic;
 145         is_signed: std_ulogic;
 146         insn: std_ulogic_vector(31 downto 0);
 147         data_len: std_ulogic_vector(3 downto 0);
 148         byte_reverse : std_ulogic;
 149         sign_extend : std_ulogic;                       -- do we need to sign extend?
 150         update : std_ulogic;                            -- is this an update instruction?
 151         reserve : std_ulogic;                           -- set for larx/stcx
 152     end record;
 153     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 154         (valid => '0', unit => NONE, insn_type => OP_ILLEGAL, bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
 155          lr => '0', rc => '0', oe => '0', invert_a => '0',
 156          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
 157          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0',
 158          byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'), read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'), cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'), others => (others => '0'));
 159
 160     type Execute1ToMultiplyType is record
 161         valid: std_ulogic;
 162         data1: std_ulogic_vector(63 downto 0);
 163         data2: std_ulogic_vector(63 downto 0);
 164         is_32bit: std_ulogic;
 165         neg_result: std_ulogic;
 166     end record;
 167     constant Execute1ToMultiplyInit : Execute1ToMultiplyType := (valid => '0',
 168                                                                  is_32bit => '0', neg_result => '0',
 169                                                                  others => (others => '0'));
 170
 171     type Execute1ToDividerType is record
 172         valid: std_ulogic;
 173         dividend: std_ulogic_vector(63 downto 0);
 174         divisor: std_ulogic_vector(63 downto 0);
 175         is_signed: std_ulogic;
 176         is_32bit: std_ulogic;
 177         is_extended: std_ulogic;
 178         is_modulus: std_ulogic;
 179         neg_result: std_ulogic;
 180     end record;
 181     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 182                                                               is_extended => '0', is_modulus => '0',
 183                                                               neg_result => '0', others => (others => '0'));
 184
 185     type Decode2ToRegisterFileType is record
 186         read1_enable : std_ulogic;
 187         read1_reg : gspr_index_t;
 188         read2_enable : std_ulogic;
 189         read2_reg : gspr_index_t;
 190         read3_enable : std_ulogic;
 191         read3_reg : gpr_index_t;
 192     end record;
 193
 194     type RegisterFileToDecode2Type is record
 195         read1_data : std_ulogic_vector(63 downto 0);
 196         read2_data : std_ulogic_vector(63 downto 0);
 197         read3_data : std_ulogic_vector(63 downto 0);
 198     end record;
 199
 200     type Decode2ToCrFileType is record
 201         read : std_ulogic;
 202     end record;
 203
 204     type CrFileToDecode2Type is record
 205         read_cr_data   : std_ulogic_vector(31 downto 0);
 206         read_xerc_data : xer_common_t;
 207     end record;
 208
 209     type Execute1ToFetch1Type is record
 210         redirect: std_ulogic;
 211         virt_mode: std_ulogic;
 212         priv_mode: std_ulogic;
 213         redirect_nia: std_ulogic_vector(63 downto 0);
 214     end record;
 215     constant Execute1ToFetch1TypeInit : Execute1ToFetch1Type := (redirect => '0', virt_mode => '0',
 216                                                                  priv_mode => '0', others => (others => '0'));
 217
 218     type Execute1ToLoadstore1Type is record
 219         valid : std_ulogic;
 220         op : insn_type_t;                               -- what ld/st or m[tf]spr or TLB op to do
 221         nia : std_ulogic_vector(63 downto 0);
 222         insn : std_ulogic_vector(31 downto 0);
 223         addr1 : std_ulogic_vector(63 downto 0);
 224         addr2 : std_ulogic_vector(63 downto 0);
 225         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 226         write_reg : gpr_index_t;
 227         length : std_ulogic_vector(3 downto 0);
 228         ci : std_ulogic;                                -- cache-inhibited load/store
 229         byte_reverse : std_ulogic;
 230         sign_extend : std_ulogic;                       -- do we need to sign extend?
 231         update : std_ulogic;                            -- is this an update instruction?
 232         update_reg : gpr_index_t;                       -- if so, the register to update
 233         xerc : xer_common_t;
 234         reserve : std_ulogic;                           -- set for larx/stcx.
 235         rc : std_ulogic;                                -- set for stcx.
 236         virt_mode : std_ulogic;                         -- do translation through TLB
 237         priv_mode : std_ulogic;                         -- privileged mode (MSR[PR] = 0)
 238     end record;
 239     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
 240                                                                      sign_extend => '0', update => '0', xerc => xerc_init,
 241                                                                      reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
 242                                                                      nia => (others => '0'), insn => (others => '0'),
 243                                                                      addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'), length => (others => '0'),
 244                                                                      others => (others => '0'));
 245
 246     type Loadstore1ToExecute1Type is record
 247         exception : std_ulogic;
 248         invalid : std_ulogic;
 249         perm_error : std_ulogic;
 250         rc_error : std_ulogic;
 251         badtree : std_ulogic;
 252         segment_fault : std_ulogic;
 253         instr_fault : std_ulogic;
 254     end record;
 255
 256     type Loadstore1ToDcacheType is record
 257         valid : std_ulogic;
 258         load : std_ulogic;                              -- is this a load
 259         dcbz : std_ulogic;
 260         nc : std_ulogic;
 261         reserve : std_ulogic;
 262         virt_mode : std_ulogic;
 263         priv_mode : std_ulogic;
 264         addr : std_ulogic_vector(63 downto 0);
 265         data : std_ulogic_vector(63 downto 0);
 266         byte_sel : std_ulogic_vector(7 downto 0);
 267     end record;
 268
 269     type DcacheToLoadstore1Type is record
 270         valid : std_ulogic;
 271         data : std_ulogic_vector(63 downto 0);
 272         store_done : std_ulogic;
 273         error : std_ulogic;
 274         cache_paradox : std_ulogic;
 275     end record;
 276
 277     type Loadstore1ToMmuType is record
 278         valid : std_ulogic;
 279         tlbie : std_ulogic;
 280         slbia : std_ulogic;
 281         mtspr : std_ulogic;
 282         iside : std_ulogic;
 283         load  : std_ulogic;
 284         priv  : std_ulogic;
 285         sprn  : std_ulogic_vector(9 downto 0);
 286         addr  : std_ulogic_vector(63 downto 0);
 287         rs    : std_ulogic_vector(63 downto 0);
 288     end record;
 289
 290     type MmuToLoadstore1Type is record
 291         done       : std_ulogic;
 292         invalid    : std_ulogic;
 293         badtree    : std_ulogic;
 294         segerr     : std_ulogic;
 295         perm_error : std_ulogic;
 296         rc_error   : std_ulogic;
 297         sprval     : std_ulogic_vector(63 downto 0);
 298     end record;
 299
 300     type MmuToDcacheType is record
 301         valid : std_ulogic;
 302         tlbie : std_ulogic;
 303         doall : std_ulogic;
 304         tlbld : std_ulogic;
 305         addr  : std_ulogic_vector(63 downto 0);
 306         pte   : std_ulogic_vector(63 downto 0);
 307     end record;
 308
 309     type DcacheToMmuType is record
 310         stall : std_ulogic;
 311         done  : std_ulogic;
 312         err   : std_ulogic;
 313         data  : std_ulogic_vector(63 downto 0);
 314     end record;
 315
 316     type MmuToIcacheType is record
 317         tlbld : std_ulogic;
 318         tlbie : std_ulogic;
 319         doall : std_ulogic;
 320         addr  : std_ulogic_vector(63 downto 0);
 321         pte   : std_ulogic_vector(63 downto 0);
 322     end record;
 323
 324     type Loadstore1ToWritebackType is record
 325         valid : std_ulogic;
 326         write_enable: std_ulogic;
 327         write_reg : gpr_index_t;
 328         write_data : std_ulogic_vector(63 downto 0);
 329         xerc : xer_common_t;
 330         rc : std_ulogic;
 331         store_done : std_ulogic;
 332     end record;
 333     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType := (valid => '0', write_enable => '0', xerc => xerc_init,
 334                                                                        rc => '0', store_done => '0', write_data => (others => '0'), others => (others => '0'));
 335
 336     type Execute1ToWritebackType is record
 337         valid: std_ulogic;
 338         rc : std_ulogic;
 339         write_enable : std_ulogic;
 340         write_reg: gspr_index_t;
 341         write_data: std_ulogic_vector(63 downto 0);
 342         write_cr_enable : std_ulogic;
 343         write_cr_mask : std_ulogic_vector(7 downto 0);
 344         write_cr_data : std_ulogic_vector(31 downto 0);
 345         write_xerc_enable : std_ulogic;
 346         xerc : xer_common_t;
 347         exc_write_enable : std_ulogic;
 348         exc_write_reg : gspr_index_t;
 349         exc_write_data : std_ulogic_vector(63 downto 0);
 350     end record;
 351     constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', write_enable => '0',
 352                                                                    write_cr_enable => '0', exc_write_enable => '0',
 353                                                                    write_xerc_enable => '0', xerc => xerc_init,
 354                                    write_data => (others => '0'), write_cr_mask => (others => '0'),
 355                                    write_cr_data => (others => '0'), write_reg => (others => '0'),
 356                                    exc_write_reg => (others => '0'), exc_write_data => (others => '0'));
 357
 358     type MultiplyToExecute1Type is record
 359         valid: std_ulogic;
 360         result: std_ulogic_vector(127 downto 0);
 361         overflow : std_ulogic;
 362     end record;
 363     constant MultiplyToExecute1Init : MultiplyToExecute1Type := (valid => '0', overflow => '0',
 364                                                                  others => (others => '0'));
 365
 366     type DividerToExecute1Type is record
 367         valid: std_ulogic;
 368         write_reg_data: std_ulogic_vector(63 downto 0);
 369         overflow : std_ulogic;
 370     end record;
 371     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 372                                                                others => (others => '0'));
 373
 374     type WritebackToRegisterFileType is record
 375         write_reg : gspr_index_t;
 376         write_data : std_ulogic_vector(63 downto 0);
 377         write_enable : std_ulogic;
 378     end record;
 379     constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
 380
 381     type WritebackToCrFileType is record
 382         write_cr_enable : std_ulogic;
 383         write_cr_mask : std_ulogic_vector(7 downto 0);
 384         write_cr_data : std_ulogic_vector(31 downto 0);
 385         write_xerc_enable : std_ulogic;
 386         write_xerc_data : xer_common_t;
 387     end record;
 388     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 389                                                                write_xerc_data => xerc_init,
 390                                                                write_cr_mask => (others => '0'),
 391                                                                write_cr_data => (others => '0'));
 392
 393 end common;
 394
 395 package body common is
 396     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 397     begin
 398         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 399     end;
 400     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 401        variable n : integer range 0 to 31;
 402        -- tmp variable introduced as workaround for VCS compilation
 403        -- simulation was failing with subtype constraint mismatch error
 404        -- see GitHub PR #173
 405        variable tmp : std_ulogic_vector(4 downto 0);
 406     begin
 407        case spr is
 408        when SPR_LR =>
 409            n := 0;
 410        when SPR_CTR =>
 411            n:= 1;
 412        when SPR_SRR0 =>
 413            n := 2;
 414        when SPR_SRR1 =>
 415            n := 3;
 416        when SPR_HSRR0 =>
 417            n := 4;
 418        when SPR_HSRR1 =>
 419            n := 5;
 420        when SPR_SPRG0 =>
 421            n := 6;
 422        when SPR_SPRG1 =>
 423            n := 7;
 424        when SPR_SPRG2 =>
 425            n := 8;
 426        when SPR_SPRG3 | SPR_SPRG3U =>
 427            n := 9;
 428        when SPR_HSPRG0 =>
 429            n := 10;
 430        when SPR_HSPRG1 =>
 431            n := 11;
 432        when SPR_XER =>
 433            n := 12;
 434        when others =>
 435            n := 0;
 436            return "000000";
 437        end case;
 438        tmp := std_ulogic_vector(to_unsigned(n, 5));
 439        return "1" & tmp;
 440     end;
 441
 442     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 443     begin
 444         return i(4 downto 0);
 445     end;
 446
 447     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 448     begin
 449         return "0" & i;
 450     end;
 451
 452     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 453     begin
 454         if s(5) = '1' then
 455             return s;
 456         else
 457             return gpr_to_gspr(g);
 458         end if;
 459     end;
 460
 461     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 462     begin
 463         return s(5);
 464     end;
 465 end common;