common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7
   8 package common is
   9
  10     -- MSR bit numbers
  11     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  12     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  13     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  14     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  15     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  16     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  17     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  18
  19     -- SPR numbers
  20     subtype spr_num_t is integer range 0 to 1023;
  21
  22     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  23
  24     constant SPR_XER    : spr_num_t := 1;
  25     constant SPR_LR     : spr_num_t := 8;
  26     constant SPR_CTR    : spr_num_t := 9;
  27     constant SPR_DSISR  : spr_num_t := 18;
  28     constant SPR_DAR    : spr_num_t := 19;
  29     constant SPR_TB     : spr_num_t := 268;
  30     constant SPR_DEC    : spr_num_t := 22;
  31     constant SPR_SRR0   : spr_num_t := 26;
  32     constant SPR_SRR1   : spr_num_t := 27;
  33     constant SPR_HSRR0  : spr_num_t := 314;
  34     constant SPR_HSRR1  : spr_num_t := 315;
  35     constant SPR_SPRG0  : spr_num_t := 272;
  36     constant SPR_SPRG1  : spr_num_t := 273;
  37     constant SPR_SPRG2  : spr_num_t := 274;
  38     constant SPR_SPRG3  : spr_num_t := 275;
  39     constant SPR_SPRG3U : spr_num_t := 259;
  40     constant SPR_HSPRG0 : spr_num_t := 304;
  41     constant SPR_HSPRG1 : spr_num_t := 305;
  42     constant SPR_PID    : spr_num_t := 48;
  43     constant SPR_PRTBL  : spr_num_t := 720;
  44
  45     -- GPR indices in the register file (GPR only)
  46     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  47
  48     -- Extended GPR indice (can hold an SPR)
  49     subtype gspr_index_t is std_ulogic_vector(5 downto 0);
  50
  51     -- Some SPRs are stored in the register file, they use the magic
  52     -- GPR numbers above 31.
  53     --
  54     -- The function fast_spr_num() returns the corresponding fast
  55     -- pseudo-GPR number for a given SPR number. The result MSB
  56     -- indicates if this is indeed a fast SPR. If clear, then
  57     -- the SPR is not stored in the GPR file.
  58     --
  59     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
  60
  61     -- Indices conversion functions
  62     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
  63     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
  64     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
  65     function is_fast_spr(s: gspr_index_t) return std_ulogic;
  66
  67     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
  68     -- in the CR file as a kind of CR extension (with a separate write
  69     -- control). The rest is stored as a fast SPR.
  70     type xer_common_t is record
  71         ca : std_ulogic;
  72         ca32 : std_ulogic;
  73         ov : std_ulogic;
  74         ov32 : std_ulogic;
  75         so : std_ulogic;
  76     end record;
  77     constant xerc_init : xer_common_t := (others => '0');
  78
  79     type irq_state_t is (WRITE_SRR0, WRITE_SRR1);
  80
  81     -- This needs to die...
  82     type ctrl_t is record
  83         tb: std_ulogic_vector(63 downto 0);
  84         dec: std_ulogic_vector(63 downto 0);
  85         msr: std_ulogic_vector(63 downto 0);
  86         irq_state : irq_state_t;
  87         irq_nia: std_ulogic_vector(63 downto 0);
  88         srr1: std_ulogic_vector(63 downto 0);
  89     end record;
  90
  91     type Fetch1ToIcacheType is record
  92         req: std_ulogic;
  93         virt_mode : std_ulogic;
  94         priv_mode : std_ulogic;
  95         stop_mark: std_ulogic;
  96         sequential: std_ulogic;
  97         nia: std_ulogic_vector(63 downto 0);
  98     end record;
  99
 100     type IcacheToDecode1Type is record
 101         valid: std_ulogic;
 102         stop_mark: std_ulogic;
 103         fetch_failed: std_ulogic;
 104         nia: std_ulogic_vector(63 downto 0);
 105         insn: std_ulogic_vector(31 downto 0);
 106     end record;
 107
 108     type Decode1ToDecode2Type is record
 109         valid: std_ulogic;
 110         stop_mark : std_ulogic;
 111         nia: std_ulogic_vector(63 downto 0);
 112         insn: std_ulogic_vector(31 downto 0);
 113         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
 114         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
 115         decode: decode_rom_t;
 116         br_pred: std_ulogic; -- Branch was predicted to be taken
 117     end record;
 118     constant Decode1ToDecode2Init : Decode1ToDecode2Type :=
 119         (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'),
 120          ispr1 => (others => '0'), ispr2 => (others => '0'), decode => decode_rom_init, br_pred => '0');
 121
 122     type Decode1ToFetch1Type is record
 123         redirect     : std_ulogic;
 124         redirect_nia : std_ulogic_vector(63 downto 0);
 125     end record;
 126
 127     type Decode2ToExecute1Type is record
 128         valid: std_ulogic;
 129         unit : unit_t;
 130         insn_type: insn_type_t;
 131         nia: std_ulogic_vector(63 downto 0);
 132         write_reg: gspr_index_t;
 133         read_reg1: gspr_index_t;
 134         read_reg2: gspr_index_t;
 135         read_data1: std_ulogic_vector(63 downto 0);
 136         read_data2: std_ulogic_vector(63 downto 0);
 137         read_data3: std_ulogic_vector(63 downto 0);
 138         bypass_data1: std_ulogic;
 139         bypass_data2: std_ulogic;
 140         bypass_data3: std_ulogic;
 141         cr: std_ulogic_vector(31 downto 0);
 142         xerc: xer_common_t;
 143         lr: std_ulogic;
 144         rc: std_ulogic;
 145         oe: std_ulogic;
 146         invert_a: std_ulogic;
 147         invert_out: std_ulogic;
 148         input_carry: carry_in_t;
 149         output_carry: std_ulogic;
 150         input_cr: std_ulogic;
 151         output_cr: std_ulogic;
 152         is_32bit: std_ulogic;
 153         is_signed: std_ulogic;
 154         insn: std_ulogic_vector(31 downto 0);
 155         data_len: std_ulogic_vector(3 downto 0);
 156         byte_reverse : std_ulogic;
 157         sign_extend : std_ulogic;                       -- do we need to sign extend?
 158         update : std_ulogic;                            -- is this an update instruction?
 159         reserve : std_ulogic;                           -- set for larx/stcx
 160         br_pred : std_ulogic;
 161     end record;
 162     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 163         (valid => '0', unit => NONE, insn_type => OP_ILLEGAL, bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
 164          lr => '0', rc => '0', oe => '0', invert_a => '0',
 165          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
 166          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0', br_pred => '0',
 167          byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'), read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'), cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'), others => (others => '0'));
 168
 169     type Execute1ToMultiplyType is record
 170         valid: std_ulogic;
 171         data1: std_ulogic_vector(63 downto 0);
 172         data2: std_ulogic_vector(63 downto 0);
 173         is_32bit: std_ulogic;
 174         neg_result: std_ulogic;
 175     end record;
 176     constant Execute1ToMultiplyInit : Execute1ToMultiplyType := (valid => '0',
 177                                                                  is_32bit => '0', neg_result => '0',
 178                                                                  others => (others => '0'));
 179
 180     type Execute1ToDividerType is record
 181         valid: std_ulogic;
 182         dividend: std_ulogic_vector(63 downto 0);
 183         divisor: std_ulogic_vector(63 downto 0);
 184         is_signed: std_ulogic;
 185         is_32bit: std_ulogic;
 186         is_extended: std_ulogic;
 187         is_modulus: std_ulogic;
 188         neg_result: std_ulogic;
 189     end record;
 190     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 191                                                               is_extended => '0', is_modulus => '0',
 192                                                               neg_result => '0', others => (others => '0'));
 193
 194     type Decode2ToRegisterFileType is record
 195         read1_enable : std_ulogic;
 196         read1_reg : gspr_index_t;
 197         read2_enable : std_ulogic;
 198         read2_reg : gspr_index_t;
 199         read3_enable : std_ulogic;
 200         read3_reg : gpr_index_t;
 201     end record;
 202
 203     type RegisterFileToDecode2Type is record
 204         read1_data : std_ulogic_vector(63 downto 0);
 205         read2_data : std_ulogic_vector(63 downto 0);
 206         read3_data : std_ulogic_vector(63 downto 0);
 207     end record;
 208
 209     type Decode2ToCrFileType is record
 210         read : std_ulogic;
 211     end record;
 212
 213     type CrFileToDecode2Type is record
 214         read_cr_data   : std_ulogic_vector(31 downto 0);
 215         read_xerc_data : xer_common_t;
 216     end record;
 217
 218     type Execute1ToFetch1Type is record
 219         redirect: std_ulogic;
 220         virt_mode: std_ulogic;
 221         priv_mode: std_ulogic;
 222         redirect_nia: std_ulogic_vector(63 downto 0);
 223     end record;
 224     constant Execute1ToFetch1TypeInit : Execute1ToFetch1Type := (redirect => '0', virt_mode => '0',
 225                                                                  priv_mode => '0', others => (others => '0'));
 226
 227     type Execute1ToLoadstore1Type is record
 228         valid : std_ulogic;
 229         op : insn_type_t;                               -- what ld/st or m[tf]spr or TLB op to do
 230         nia : std_ulogic_vector(63 downto 0);
 231         insn : std_ulogic_vector(31 downto 0);
 232         addr1 : std_ulogic_vector(63 downto 0);
 233         addr2 : std_ulogic_vector(63 downto 0);
 234         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 235         write_reg : gpr_index_t;
 236         length : std_ulogic_vector(3 downto 0);
 237         ci : std_ulogic;                                -- cache-inhibited load/store
 238         byte_reverse : std_ulogic;
 239         sign_extend : std_ulogic;                       -- do we need to sign extend?
 240         update : std_ulogic;                            -- is this an update instruction?
 241         update_reg : gpr_index_t;                       -- if so, the register to update
 242         xerc : xer_common_t;
 243         reserve : std_ulogic;                           -- set for larx/stcx.
 244         rc : std_ulogic;                                -- set for stcx.
 245         virt_mode : std_ulogic;                         -- do translation through TLB
 246         priv_mode : std_ulogic;                         -- privileged mode (MSR[PR] = 0)
 247     end record;
 248     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
 249                                                                      sign_extend => '0', update => '0', xerc => xerc_init,
 250                                                                      reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
 251                                                                      nia => (others => '0'), insn => (others => '0'),
 252                                                                      addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'), length => (others => '0'),
 253                                                                      others => (others => '0'));
 254
 255     type Loadstore1ToExecute1Type is record
 256         busy : std_ulogic;
 257         exception : std_ulogic;
 258         invalid : std_ulogic;
 259         perm_error : std_ulogic;
 260         rc_error : std_ulogic;
 261         badtree : std_ulogic;
 262         segment_fault : std_ulogic;
 263         instr_fault : std_ulogic;
 264     end record;
 265
 266     type Loadstore1ToDcacheType is record
 267         valid : std_ulogic;
 268         load : std_ulogic;                              -- is this a load
 269         dcbz : std_ulogic;
 270         nc : std_ulogic;
 271         reserve : std_ulogic;
 272         virt_mode : std_ulogic;
 273         priv_mode : std_ulogic;
 274         addr : std_ulogic_vector(63 downto 0);
 275         data : std_ulogic_vector(63 downto 0);
 276         byte_sel : std_ulogic_vector(7 downto 0);
 277     end record;
 278
 279     type DcacheToLoadstore1Type is record
 280         valid : std_ulogic;
 281         data : std_ulogic_vector(63 downto 0);
 282         store_done : std_ulogic;
 283         error : std_ulogic;
 284         cache_paradox : std_ulogic;
 285     end record;
 286
 287     type Loadstore1ToMmuType is record
 288         valid : std_ulogic;
 289         tlbie : std_ulogic;
 290         slbia : std_ulogic;
 291         mtspr : std_ulogic;
 292         iside : std_ulogic;
 293         load  : std_ulogic;
 294         priv  : std_ulogic;
 295         sprn  : std_ulogic_vector(9 downto 0);
 296         addr  : std_ulogic_vector(63 downto 0);
 297         rs    : std_ulogic_vector(63 downto 0);
 298     end record;
 299
 300     type MmuToLoadstore1Type is record
 301         done       : std_ulogic;
 302         invalid    : std_ulogic;
 303         badtree    : std_ulogic;
 304         segerr     : std_ulogic;
 305         perm_error : std_ulogic;
 306         rc_error   : std_ulogic;
 307         sprval     : std_ulogic_vector(63 downto 0);
 308     end record;
 309
 310     type MmuToDcacheType is record
 311         valid : std_ulogic;
 312         tlbie : std_ulogic;
 313         doall : std_ulogic;
 314         tlbld : std_ulogic;
 315         addr  : std_ulogic_vector(63 downto 0);
 316         pte   : std_ulogic_vector(63 downto 0);
 317     end record;
 318
 319     type DcacheToMmuType is record
 320         stall : std_ulogic;
 321         done  : std_ulogic;
 322         err   : std_ulogic;
 323         data  : std_ulogic_vector(63 downto 0);
 324     end record;
 325
 326     type MmuToIcacheType is record
 327         tlbld : std_ulogic;
 328         tlbie : std_ulogic;
 329         doall : std_ulogic;
 330         addr  : std_ulogic_vector(63 downto 0);
 331         pte   : std_ulogic_vector(63 downto 0);
 332     end record;
 333
 334     type Loadstore1ToWritebackType is record
 335         valid : std_ulogic;
 336         write_enable: std_ulogic;
 337         write_reg : gpr_index_t;
 338         write_data : std_ulogic_vector(63 downto 0);
 339         xerc : xer_common_t;
 340         rc : std_ulogic;
 341         store_done : std_ulogic;
 342     end record;
 343     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType := (valid => '0', write_enable => '0', xerc => xerc_init,
 344                                                                        rc => '0', store_done => '0', write_data => (others => '0'), others => (others => '0'));
 345
 346     type Execute1ToWritebackType is record
 347         valid: std_ulogic;
 348         rc : std_ulogic;
 349         write_enable : std_ulogic;
 350         write_reg: gspr_index_t;
 351         write_data: std_ulogic_vector(63 downto 0);
 352         write_cr_enable : std_ulogic;
 353         write_cr_mask : std_ulogic_vector(7 downto 0);
 354         write_cr_data : std_ulogic_vector(31 downto 0);
 355         write_xerc_enable : std_ulogic;
 356         xerc : xer_common_t;
 357         exc_write_enable : std_ulogic;
 358         exc_write_reg : gspr_index_t;
 359         exc_write_data : std_ulogic_vector(63 downto 0);
 360     end record;
 361     constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', write_enable => '0',
 362                                                                    write_cr_enable => '0', exc_write_enable => '0',
 363                                                                    write_xerc_enable => '0', xerc => xerc_init,
 364                                    write_data => (others => '0'), write_cr_mask => (others => '0'),
 365                                    write_cr_data => (others => '0'), write_reg => (others => '0'),
 366                                    exc_write_reg => (others => '0'), exc_write_data => (others => '0'));
 367
 368     type MultiplyToExecute1Type is record
 369         valid: std_ulogic;
 370         result: std_ulogic_vector(127 downto 0);
 371         overflow : std_ulogic;
 372     end record;
 373     constant MultiplyToExecute1Init : MultiplyToExecute1Type := (valid => '0', overflow => '0',
 374                                                                  others => (others => '0'));
 375
 376     type DividerToExecute1Type is record
 377         valid: std_ulogic;
 378         write_reg_data: std_ulogic_vector(63 downto 0);
 379         overflow : std_ulogic;
 380     end record;
 381     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 382                                                                others => (others => '0'));
 383
 384     type WritebackToRegisterFileType is record
 385         write_reg : gspr_index_t;
 386         write_data : std_ulogic_vector(63 downto 0);
 387         write_enable : std_ulogic;
 388     end record;
 389     constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
 390
 391     type WritebackToCrFileType is record
 392         write_cr_enable : std_ulogic;
 393         write_cr_mask : std_ulogic_vector(7 downto 0);
 394         write_cr_data : std_ulogic_vector(31 downto 0);
 395         write_xerc_enable : std_ulogic;
 396         write_xerc_data : xer_common_t;
 397     end record;
 398     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 399                                                                write_xerc_data => xerc_init,
 400                                                                write_cr_mask => (others => '0'),
 401                                                                write_cr_data => (others => '0'));
 402
 403 end common;
 404
 405 package body common is
 406     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 407     begin
 408         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 409     end;
 410     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 411        variable n : integer range 0 to 31;
 412        -- tmp variable introduced as workaround for VCS compilation
 413        -- simulation was failing with subtype constraint mismatch error
 414        -- see GitHub PR #173
 415        variable tmp : std_ulogic_vector(4 downto 0);
 416     begin
 417        case spr is
 418        when SPR_LR =>
 419            n := 0;
 420        when SPR_CTR =>
 421            n:= 1;
 422        when SPR_SRR0 =>
 423            n := 2;
 424        when SPR_SRR1 =>
 425            n := 3;
 426        when SPR_HSRR0 =>
 427            n := 4;
 428        when SPR_HSRR1 =>
 429            n := 5;
 430        when SPR_SPRG0 =>
 431            n := 6;
 432        when SPR_SPRG1 =>
 433            n := 7;
 434        when SPR_SPRG2 =>
 435            n := 8;
 436        when SPR_SPRG3 | SPR_SPRG3U =>
 437            n := 9;
 438        when SPR_HSPRG0 =>
 439            n := 10;
 440        when SPR_HSPRG1 =>
 441            n := 11;
 442        when SPR_XER =>
 443            n := 12;
 444        when others =>
 445            n := 0;
 446            return "000000";
 447        end case;
 448        tmp := std_ulogic_vector(to_unsigned(n, 5));
 449        return "1" & tmp;
 450     end;
 451
 452     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 453     begin
 454         return i(4 downto 0);
 455     end;
 456
 457     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 458     begin
 459         return "0" & i;
 460     end;
 461
 462     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 463     begin
 464         if s(5) = '1' then
 465             return s;
 466         else
 467             return gpr_to_gspr(g);
 468         end if;
 469     end;
 470
 471     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 472     begin
 473         return s(5);
 474     end;
 475 end common;