common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7
   8 package common is
   9
  10     -- MSR bit numbers
  11     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  12     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  13     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  14     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  15     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  16     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  17     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  18
  19     -- SPR numbers
  20     subtype spr_num_t is integer range 0 to 1023;
  21
  22     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  23
  24     constant SPR_XER    : spr_num_t := 1;
  25     constant SPR_LR     : spr_num_t := 8;
  26     constant SPR_CTR    : spr_num_t := 9;
  27     constant SPR_DSISR  : spr_num_t := 18;
  28     constant SPR_DAR    : spr_num_t := 19;
  29     constant SPR_TB     : spr_num_t := 268;
  30     constant SPR_DEC    : spr_num_t := 22;
  31     constant SPR_SRR0   : spr_num_t := 26;
  32     constant SPR_SRR1   : spr_num_t := 27;
  33     constant SPR_HSRR0  : spr_num_t := 314;
  34     constant SPR_HSRR1  : spr_num_t := 315;
  35     constant SPR_SPRG0  : spr_num_t := 272;
  36     constant SPR_SPRG1  : spr_num_t := 273;
  37     constant SPR_SPRG2  : spr_num_t := 274;
  38     constant SPR_SPRG3  : spr_num_t := 275;
  39     constant SPR_SPRG3U : spr_num_t := 259;
  40     constant SPR_HSPRG0 : spr_num_t := 304;
  41     constant SPR_HSPRG1 : spr_num_t := 305;
  42     constant SPR_PID    : spr_num_t := 48;
  43     constant SPR_PRTBL  : spr_num_t := 720;
  44
  45     -- GPR indices in the register file (GPR only)
  46     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  47
  48     -- Extended GPR indice (can hold an SPR)
  49     subtype gspr_index_t is std_ulogic_vector(5 downto 0);
  50
  51     -- Some SPRs are stored in the register file, they use the magic
  52     -- GPR numbers above 31.
  53     --
  54     -- The function fast_spr_num() returns the corresponding fast
  55     -- pseudo-GPR number for a given SPR number. The result MSB
  56     -- indicates if this is indeed a fast SPR. If clear, then
  57     -- the SPR is not stored in the GPR file.
  58     --
  59     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
  60
  61     -- Indices conversion functions
  62     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
  63     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
  64     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
  65     function is_fast_spr(s: gspr_index_t) return std_ulogic;
  66
  67     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
  68     -- in the CR file as a kind of CR extension (with a separate write
  69     -- control). The rest is stored as a fast SPR.
  70     type xer_common_t is record
  71         ca : std_ulogic;
  72         ca32 : std_ulogic;
  73         ov : std_ulogic;
  74         ov32 : std_ulogic;
  75         so : std_ulogic;
  76     end record;
  77     constant xerc_init : xer_common_t := (others => '0');
  78
  79     type irq_state_t is (WRITE_SRR0, WRITE_SRR1);
  80
  81     -- For now, fixed 16 sources, make this either a parametric
  82     -- package of some sort or an unconstrainted array.
  83     type ics_to_icp_t is record
  84         -- Level interrupts only, ICS just keeps prsenting the
  85         -- highest priority interrupt. Once handling edge, something
  86         -- smarter involving handshake & reject support will be needed
  87         src : std_ulogic_vector(3 downto 0);
  88         pri : std_ulogic_vector(7 downto 0);
  89     end record;
  90
  91     -- This needs to die...
  92     type ctrl_t is record
  93         tb: std_ulogic_vector(63 downto 0);
  94         dec: std_ulogic_vector(63 downto 0);
  95         msr: std_ulogic_vector(63 downto 0);
  96         irq_state : irq_state_t;
  97         irq_nia: std_ulogic_vector(63 downto 0);
  98         srr1: std_ulogic_vector(63 downto 0);
  99     end record;
 100
 101     type Fetch1ToIcacheType is record
 102         req: std_ulogic;
 103         virt_mode : std_ulogic;
 104         priv_mode : std_ulogic;
 105         stop_mark: std_ulogic;
 106         sequential: std_ulogic;
 107         nia: std_ulogic_vector(63 downto 0);
 108     end record;
 109
 110     type IcacheToDecode1Type is record
 111         valid: std_ulogic;
 112         stop_mark: std_ulogic;
 113         fetch_failed: std_ulogic;
 114         nia: std_ulogic_vector(63 downto 0);
 115         insn: std_ulogic_vector(31 downto 0);
 116     end record;
 117
 118     type Decode1ToDecode2Type is record
 119         valid: std_ulogic;
 120         stop_mark : std_ulogic;
 121         nia: std_ulogic_vector(63 downto 0);
 122         insn: std_ulogic_vector(31 downto 0);
 123         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
 124         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
 125         decode: decode_rom_t;
 126         br_pred: std_ulogic; -- Branch was predicted to be taken
 127     end record;
 128     constant Decode1ToDecode2Init : Decode1ToDecode2Type :=
 129         (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'),
 130          ispr1 => (others => '0'), ispr2 => (others => '0'), decode => decode_rom_init, br_pred => '0');
 131
 132     type Decode1ToFetch1Type is record
 133         redirect     : std_ulogic;
 134         redirect_nia : std_ulogic_vector(63 downto 0);
 135     end record;
 136
 137     type Decode2ToExecute1Type is record
 138         valid: std_ulogic;
 139         unit : unit_t;
 140         insn_type: insn_type_t;
 141         nia: std_ulogic_vector(63 downto 0);
 142         write_reg: gspr_index_t;
 143         read_reg1: gspr_index_t;
 144         read_reg2: gspr_index_t;
 145         read_data1: std_ulogic_vector(63 downto 0);
 146         read_data2: std_ulogic_vector(63 downto 0);
 147         read_data3: std_ulogic_vector(63 downto 0);
 148         bypass_data1: std_ulogic;
 149         bypass_data2: std_ulogic;
 150         bypass_data3: std_ulogic;
 151         cr: std_ulogic_vector(31 downto 0);
 152         xerc: xer_common_t;
 153         lr: std_ulogic;
 154         rc: std_ulogic;
 155         oe: std_ulogic;
 156         invert_a: std_ulogic;
 157         invert_out: std_ulogic;
 158         input_carry: carry_in_t;
 159         output_carry: std_ulogic;
 160         input_cr: std_ulogic;
 161         output_cr: std_ulogic;
 162         is_32bit: std_ulogic;
 163         is_signed: std_ulogic;
 164         insn: std_ulogic_vector(31 downto 0);
 165         data_len: std_ulogic_vector(3 downto 0);
 166         byte_reverse : std_ulogic;
 167         sign_extend : std_ulogic;                       -- do we need to sign extend?
 168         update : std_ulogic;                            -- is this an update instruction?
 169         reserve : std_ulogic;                           -- set for larx/stcx
 170         br_pred : std_ulogic;
 171     end record;
 172     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 173         (valid => '0', unit => NONE, insn_type => OP_ILLEGAL, bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
 174          lr => '0', rc => '0', oe => '0', invert_a => '0',
 175          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
 176          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0', br_pred => '0',
 177          byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'), read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'), cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'), others => (others => '0'));
 178
 179     type Execute1ToMultiplyType is record
 180         valid: std_ulogic;
 181         data1: std_ulogic_vector(63 downto 0);
 182         data2: std_ulogic_vector(63 downto 0);
 183         is_32bit: std_ulogic;
 184         neg_result: std_ulogic;
 185     end record;
 186     constant Execute1ToMultiplyInit : Execute1ToMultiplyType := (valid => '0',
 187                                                                  is_32bit => '0', neg_result => '0',
 188                                                                  others => (others => '0'));
 189
 190     type Execute1ToDividerType is record
 191         valid: std_ulogic;
 192         dividend: std_ulogic_vector(63 downto 0);
 193         divisor: std_ulogic_vector(63 downto 0);
 194         is_signed: std_ulogic;
 195         is_32bit: std_ulogic;
 196         is_extended: std_ulogic;
 197         is_modulus: std_ulogic;
 198         neg_result: std_ulogic;
 199     end record;
 200     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 201                                                               is_extended => '0', is_modulus => '0',
 202                                                               neg_result => '0', others => (others => '0'));
 203
 204     type Decode2ToRegisterFileType is record
 205         read1_enable : std_ulogic;
 206         read1_reg : gspr_index_t;
 207         read2_enable : std_ulogic;
 208         read2_reg : gspr_index_t;
 209         read3_enable : std_ulogic;
 210         read3_reg : gpr_index_t;
 211     end record;
 212
 213     type RegisterFileToDecode2Type is record
 214         read1_data : std_ulogic_vector(63 downto 0);
 215         read2_data : std_ulogic_vector(63 downto 0);
 216         read3_data : std_ulogic_vector(63 downto 0);
 217     end record;
 218
 219     type Decode2ToCrFileType is record
 220         read : std_ulogic;
 221     end record;
 222
 223     type CrFileToDecode2Type is record
 224         read_cr_data   : std_ulogic_vector(31 downto 0);
 225         read_xerc_data : xer_common_t;
 226     end record;
 227
 228     type Execute1ToFetch1Type is record
 229         redirect: std_ulogic;
 230         virt_mode: std_ulogic;
 231         priv_mode: std_ulogic;
 232         redirect_nia: std_ulogic_vector(63 downto 0);
 233     end record;
 234     constant Execute1ToFetch1TypeInit : Execute1ToFetch1Type := (redirect => '0', virt_mode => '0',
 235                                                                  priv_mode => '0', others => (others => '0'));
 236
 237     type Execute1ToLoadstore1Type is record
 238         valid : std_ulogic;
 239         op : insn_type_t;                               -- what ld/st or m[tf]spr or TLB op to do
 240         nia : std_ulogic_vector(63 downto 0);
 241         insn : std_ulogic_vector(31 downto 0);
 242         addr1 : std_ulogic_vector(63 downto 0);
 243         addr2 : std_ulogic_vector(63 downto 0);
 244         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 245         write_reg : gpr_index_t;
 246         length : std_ulogic_vector(3 downto 0);
 247         ci : std_ulogic;                                -- cache-inhibited load/store
 248         byte_reverse : std_ulogic;
 249         sign_extend : std_ulogic;                       -- do we need to sign extend?
 250         update : std_ulogic;                            -- is this an update instruction?
 251         update_reg : gpr_index_t;                       -- if so, the register to update
 252         xerc : xer_common_t;
 253         reserve : std_ulogic;                           -- set for larx/stcx.
 254         rc : std_ulogic;                                -- set for stcx.
 255         virt_mode : std_ulogic;                         -- do translation through TLB
 256         priv_mode : std_ulogic;                         -- privileged mode (MSR[PR] = 0)
 257     end record;
 258     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
 259                                                                      sign_extend => '0', update => '0', xerc => xerc_init,
 260                                                                      reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
 261                                                                      nia => (others => '0'), insn => (others => '0'),
 262                                                                      addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'), length => (others => '0'),
 263                                                                      others => (others => '0'));
 264
 265     type Loadstore1ToExecute1Type is record
 266         busy : std_ulogic;
 267         exception : std_ulogic;
 268         invalid : std_ulogic;
 269         perm_error : std_ulogic;
 270         rc_error : std_ulogic;
 271         badtree : std_ulogic;
 272         segment_fault : std_ulogic;
 273         instr_fault : std_ulogic;
 274     end record;
 275
 276     type Loadstore1ToDcacheType is record
 277         valid : std_ulogic;
 278         load : std_ulogic;                              -- is this a load
 279         dcbz : std_ulogic;
 280         nc : std_ulogic;
 281         reserve : std_ulogic;
 282         virt_mode : std_ulogic;
 283         priv_mode : std_ulogic;
 284         addr : std_ulogic_vector(63 downto 0);
 285         data : std_ulogic_vector(63 downto 0);
 286         byte_sel : std_ulogic_vector(7 downto 0);
 287     end record;
 288
 289     type DcacheToLoadstore1Type is record
 290         valid : std_ulogic;
 291         data : std_ulogic_vector(63 downto 0);
 292         store_done : std_ulogic;
 293         error : std_ulogic;
 294         cache_paradox : std_ulogic;
 295     end record;
 296
 297     type Loadstore1ToMmuType is record
 298         valid : std_ulogic;
 299         tlbie : std_ulogic;
 300         slbia : std_ulogic;
 301         mtspr : std_ulogic;
 302         iside : std_ulogic;
 303         load  : std_ulogic;
 304         priv  : std_ulogic;
 305         sprn  : std_ulogic_vector(9 downto 0);
 306         addr  : std_ulogic_vector(63 downto 0);
 307         rs    : std_ulogic_vector(63 downto 0);
 308     end record;
 309
 310     type MmuToLoadstore1Type is record
 311         done       : std_ulogic;
 312         invalid    : std_ulogic;
 313         badtree    : std_ulogic;
 314         segerr     : std_ulogic;
 315         perm_error : std_ulogic;
 316         rc_error   : std_ulogic;
 317         sprval     : std_ulogic_vector(63 downto 0);
 318     end record;
 319
 320     type MmuToDcacheType is record
 321         valid : std_ulogic;
 322         tlbie : std_ulogic;
 323         doall : std_ulogic;
 324         tlbld : std_ulogic;
 325         addr  : std_ulogic_vector(63 downto 0);
 326         pte   : std_ulogic_vector(63 downto 0);
 327     end record;
 328
 329     type DcacheToMmuType is record
 330         stall : std_ulogic;
 331         done  : std_ulogic;
 332         err   : std_ulogic;
 333         data  : std_ulogic_vector(63 downto 0);
 334     end record;
 335
 336     type MmuToIcacheType is record
 337         tlbld : std_ulogic;
 338         tlbie : std_ulogic;
 339         doall : std_ulogic;
 340         addr  : std_ulogic_vector(63 downto 0);
 341         pte   : std_ulogic_vector(63 downto 0);
 342     end record;
 343
 344     type Loadstore1ToWritebackType is record
 345         valid : std_ulogic;
 346         write_enable: std_ulogic;
 347         write_reg : gpr_index_t;
 348         write_data : std_ulogic_vector(63 downto 0);
 349         xerc : xer_common_t;
 350         rc : std_ulogic;
 351         store_done : std_ulogic;
 352     end record;
 353     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType := (valid => '0', write_enable => '0', xerc => xerc_init,
 354                                                                        rc => '0', store_done => '0', write_data => (others => '0'), others => (others => '0'));
 355
 356     type Execute1ToWritebackType is record
 357         valid: std_ulogic;
 358         rc : std_ulogic;
 359         write_enable : std_ulogic;
 360         write_reg: gspr_index_t;
 361         write_data: std_ulogic_vector(63 downto 0);
 362         write_cr_enable : std_ulogic;
 363         write_cr_mask : std_ulogic_vector(7 downto 0);
 364         write_cr_data : std_ulogic_vector(31 downto 0);
 365         write_xerc_enable : std_ulogic;
 366         xerc : xer_common_t;
 367         exc_write_enable : std_ulogic;
 368         exc_write_reg : gspr_index_t;
 369         exc_write_data : std_ulogic_vector(63 downto 0);
 370     end record;
 371     constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', write_enable => '0',
 372                                                                    write_cr_enable => '0', exc_write_enable => '0',
 373                                                                    write_xerc_enable => '0', xerc => xerc_init,
 374                                    write_data => (others => '0'), write_cr_mask => (others => '0'),
 375                                    write_cr_data => (others => '0'), write_reg => (others => '0'),
 376                                    exc_write_reg => (others => '0'), exc_write_data => (others => '0'));
 377
 378     type MultiplyToExecute1Type is record
 379         valid: std_ulogic;
 380         result: std_ulogic_vector(127 downto 0);
 381         overflow : std_ulogic;
 382     end record;
 383     constant MultiplyToExecute1Init : MultiplyToExecute1Type := (valid => '0', overflow => '0',
 384                                                                  others => (others => '0'));
 385
 386     type DividerToExecute1Type is record
 387         valid: std_ulogic;
 388         write_reg_data: std_ulogic_vector(63 downto 0);
 389         overflow : std_ulogic;
 390     end record;
 391     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 392                                                                others => (others => '0'));
 393
 394     type WritebackToRegisterFileType is record
 395         write_reg : gspr_index_t;
 396         write_data : std_ulogic_vector(63 downto 0);
 397         write_enable : std_ulogic;
 398     end record;
 399     constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
 400
 401     type WritebackToCrFileType is record
 402         write_cr_enable : std_ulogic;
 403         write_cr_mask : std_ulogic_vector(7 downto 0);
 404         write_cr_data : std_ulogic_vector(31 downto 0);
 405         write_xerc_enable : std_ulogic;
 406         write_xerc_data : xer_common_t;
 407     end record;
 408     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 409                                                                write_xerc_data => xerc_init,
 410                                                                write_cr_mask => (others => '0'),
 411                                                                write_cr_data => (others => '0'));
 412
 413 end common;
 414
 415 package body common is
 416     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 417     begin
 418         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 419     end;
 420     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 421        variable n : integer range 0 to 31;
 422        -- tmp variable introduced as workaround for VCS compilation
 423        -- simulation was failing with subtype constraint mismatch error
 424        -- see GitHub PR #173
 425        variable tmp : std_ulogic_vector(4 downto 0);
 426     begin
 427        case spr is
 428        when SPR_LR =>
 429            n := 0;
 430        when SPR_CTR =>
 431            n:= 1;
 432        when SPR_SRR0 =>
 433            n := 2;
 434        when SPR_SRR1 =>
 435            n := 3;
 436        when SPR_HSRR0 =>
 437            n := 4;
 438        when SPR_HSRR1 =>
 439            n := 5;
 440        when SPR_SPRG0 =>
 441            n := 6;
 442        when SPR_SPRG1 =>
 443            n := 7;
 444        when SPR_SPRG2 =>
 445            n := 8;
 446        when SPR_SPRG3 | SPR_SPRG3U =>
 447            n := 9;
 448        when SPR_HSPRG0 =>
 449            n := 10;
 450        when SPR_HSPRG1 =>
 451            n := 11;
 452        when SPR_XER =>
 453            n := 12;
 454        when others =>
 455            n := 0;
 456            return "000000";
 457        end case;
 458        tmp := std_ulogic_vector(to_unsigned(n, 5));
 459        return "1" & tmp;
 460     end;
 461
 462     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 463     begin
 464         return i(4 downto 0);
 465     end;
 466
 467     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 468     begin
 469         return "0" & i;
 470     end;
 471
 472     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 473     begin
 474         if s(5) = '1' then
 475             return s;
 476         else
 477             return gpr_to_gspr(g);
 478         end if;
 479     end;
 480
 481     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 482     begin
 483         return s(5);
 484     end;
 485 end common;