common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7
   8 package common is
   9
  10     -- MSR bit numbers
  11     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  12     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  13     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  14     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  15     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  16     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  17     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  18
  19     -- SPR numbers
  20     subtype spr_num_t is integer range 0 to 1023;
  21
  22     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  23
  24     constant SPR_XER    : spr_num_t := 1;
  25     constant SPR_LR     : spr_num_t := 8;
  26     constant SPR_CTR    : spr_num_t := 9;
  27     constant SPR_DSISR  : spr_num_t := 18;
  28     constant SPR_DAR    : spr_num_t := 19;
  29     constant SPR_TB     : spr_num_t := 268;
  30     constant SPR_DEC    : spr_num_t := 22;
  31     constant SPR_SRR0   : spr_num_t := 26;
  32     constant SPR_SRR1   : spr_num_t := 27;
  33     constant SPR_HSRR0  : spr_num_t := 314;
  34     constant SPR_HSRR1  : spr_num_t := 315;
  35     constant SPR_SPRG0  : spr_num_t := 272;
  36     constant SPR_SPRG1  : spr_num_t := 273;
  37     constant SPR_SPRG2  : spr_num_t := 274;
  38     constant SPR_SPRG3  : spr_num_t := 275;
  39     constant SPR_SPRG3U : spr_num_t := 259;
  40     constant SPR_HSPRG0 : spr_num_t := 304;
  41     constant SPR_HSPRG1 : spr_num_t := 305;
  42     constant SPR_PID    : spr_num_t := 48;
  43     constant SPR_PRTBL  : spr_num_t := 720;
  44
  45     -- GPR indices in the register file (GPR only)
  46     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  47
  48     -- Extended GPR indice (can hold an SPR)
  49     subtype gspr_index_t is std_ulogic_vector(5 downto 0);
  50
  51     -- Some SPRs are stored in the register file, they use the magic
  52     -- GPR numbers above 31.
  53     --
  54     -- The function fast_spr_num() returns the corresponding fast
  55     -- pseudo-GPR number for a given SPR number. The result MSB
  56     -- indicates if this is indeed a fast SPR. If clear, then
  57     -- the SPR is not stored in the GPR file.
  58     --
  59     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
  60
  61     -- Indices conversion functions
  62     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
  63     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
  64     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
  65     function is_fast_spr(s: gspr_index_t) return std_ulogic;
  66
  67     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
  68     -- in the CR file as a kind of CR extension (with a separate write
  69     -- control). The rest is stored as a fast SPR.
  70     type xer_common_t is record
  71         ca : std_ulogic;
  72         ca32 : std_ulogic;
  73         ov : std_ulogic;
  74         ov32 : std_ulogic;
  75         so : std_ulogic;
  76     end record;
  77     constant xerc_init : xer_common_t := (others => '0');
  78
  79     type irq_state_t is (WRITE_SRR0, WRITE_SRR1);
  80
  81     -- This needs to die...
  82     type ctrl_t is record
  83         tb: std_ulogic_vector(63 downto 0);
  84         dec: std_ulogic_vector(63 downto 0);
  85         msr: std_ulogic_vector(63 downto 0);
  86         irq_state : irq_state_t;
  87         irq_nia: std_ulogic_vector(63 downto 0);
  88         srr1: std_ulogic_vector(63 downto 0);
  89     end record;
  90
  91     type Fetch1ToIcacheType is record
  92         req: std_ulogic;
  93         virt_mode : std_ulogic;
  94         priv_mode : std_ulogic;
  95         stop_mark: std_ulogic;
  96         nia: std_ulogic_vector(63 downto 0);
  97     end record;
  98
  99     type IcacheToFetch2Type is record
 100         valid: std_ulogic;
 101         stop_mark: std_ulogic;
 102         fetch_failed: std_ulogic;
 103         nia: std_ulogic_vector(63 downto 0);
 104         insn: std_ulogic_vector(31 downto 0);
 105     end record;
 106
 107     type Fetch2ToDecode1Type is record
 108         valid: std_ulogic;
 109         stop_mark : std_ulogic;
 110         fetch_failed: std_ulogic;
 111         nia: std_ulogic_vector(63 downto 0);
 112         insn: std_ulogic_vector(31 downto 0);
 113     end record;
 114     constant Fetch2ToDecode1Init : Fetch2ToDecode1Type := (valid => '0', stop_mark => '0', fetch_failed => '0',
 115                                                            nia => (others => '0'), insn => (others => '0'));
 116
 117     type Decode1ToDecode2Type is record
 118         valid: std_ulogic;
 119         stop_mark : std_ulogic;
 120         nia: std_ulogic_vector(63 downto 0);
 121         insn: std_ulogic_vector(31 downto 0);
 122         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
 123         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
 124         decode: decode_rom_t;
 125     end record;
 126     constant Decode1ToDecode2Init : Decode1ToDecode2Type := (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'), ispr1 => (others => '0'), ispr2 => (others => '0'), decode => decode_rom_init);
 127
 128     type Decode2ToExecute1Type is record
 129         valid: std_ulogic;
 130         unit : unit_t;
 131         insn_type: insn_type_t;
 132         nia: std_ulogic_vector(63 downto 0);
 133         write_reg: gspr_index_t;
 134         read_reg1: gspr_index_t;
 135         read_reg2: gspr_index_t;
 136         read_data1: std_ulogic_vector(63 downto 0);
 137         read_data2: std_ulogic_vector(63 downto 0);
 138         read_data3: std_ulogic_vector(63 downto 0);
 139         bypass_data1: std_ulogic;
 140         bypass_data2: std_ulogic;
 141         bypass_data3: std_ulogic;
 142         cr: std_ulogic_vector(31 downto 0);
 143         xerc: xer_common_t;
 144         lr: std_ulogic;
 145         rc: std_ulogic;
 146         oe: std_ulogic;
 147         invert_a: std_ulogic;
 148         invert_out: std_ulogic;
 149         input_carry: carry_in_t;
 150         output_carry: std_ulogic;
 151         input_cr: std_ulogic;
 152         output_cr: std_ulogic;
 153         is_32bit: std_ulogic;
 154         is_signed: std_ulogic;
 155         insn: std_ulogic_vector(31 downto 0);
 156         data_len: std_ulogic_vector(3 downto 0);
 157         byte_reverse : std_ulogic;
 158         sign_extend : std_ulogic;                       -- do we need to sign extend?
 159         update : std_ulogic;                            -- is this an update instruction?
 160         reserve : std_ulogic;                           -- set for larx/stcx
 161     end record;
 162     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 163         (valid => '0', unit => NONE, insn_type => OP_ILLEGAL, bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
 164          lr => '0', rc => '0', oe => '0', invert_a => '0',
 165          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
 166          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0',
 167          byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'), read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'), cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'), others => (others => '0'));
 168
 169     type Execute1ToMultiplyType is record
 170         valid: std_ulogic;
 171         insn_type: insn_type_t;
 172         data1: std_ulogic_vector(64 downto 0);
 173         data2: std_ulogic_vector(64 downto 0);
 174         is_32bit: std_ulogic;
 175     end record;
 176     constant Execute1ToMultiplyInit : Execute1ToMultiplyType := (valid => '0', insn_type => OP_ILLEGAL,
 177                                                                  is_32bit => '0',
 178                                                                  others => (others => '0'));
 179
 180     type Execute1ToDividerType is record
 181         valid: std_ulogic;
 182         dividend: std_ulogic_vector(63 downto 0);
 183         divisor: std_ulogic_vector(63 downto 0);
 184         is_signed: std_ulogic;
 185         is_32bit: std_ulogic;
 186         is_extended: std_ulogic;
 187         is_modulus: std_ulogic;
 188         neg_result: std_ulogic;
 189     end record;
 190     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 191                                                               is_extended => '0', is_modulus => '0',
 192                                                               neg_result => '0', others => (others => '0'));
 193
 194     type Decode2ToRegisterFileType is record
 195         read1_enable : std_ulogic;
 196         read1_reg : gspr_index_t;
 197         read2_enable : std_ulogic;
 198         read2_reg : gspr_index_t;
 199         read3_enable : std_ulogic;
 200         read3_reg : gpr_index_t;
 201     end record;
 202
 203     type RegisterFileToDecode2Type is record
 204         read1_data : std_ulogic_vector(63 downto 0);
 205         read2_data : std_ulogic_vector(63 downto 0);
 206         read3_data : std_ulogic_vector(63 downto 0);
 207     end record;
 208
 209     type Decode2ToCrFileType is record
 210         read : std_ulogic;
 211     end record;
 212
 213     type CrFileToDecode2Type is record
 214         read_cr_data   : std_ulogic_vector(31 downto 0);
 215         read_xerc_data : xer_common_t;
 216     end record;
 217
 218     type Execute1ToFetch1Type is record
 219         redirect: std_ulogic;
 220         virt_mode: std_ulogic;
 221         priv_mode: std_ulogic;
 222         redirect_nia: std_ulogic_vector(63 downto 0);
 223     end record;
 224     constant Execute1ToFetch1TypeInit : Execute1ToFetch1Type := (redirect => '0', virt_mode => '0',
 225                                                                  priv_mode => '0', others => (others => '0'));
 226
 227     type Execute1ToLoadstore1Type is record
 228         valid : std_ulogic;
 229         op : insn_type_t;                               -- what ld/st or m[tf]spr or TLB op to do
 230         nia : std_ulogic_vector(63 downto 0);
 231         insn : std_ulogic_vector(31 downto 0);
 232         addr1 : std_ulogic_vector(63 downto 0);
 233         addr2 : std_ulogic_vector(63 downto 0);
 234         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 235         write_reg : gpr_index_t;
 236         length : std_ulogic_vector(3 downto 0);
 237         ci : std_ulogic;                                -- cache-inhibited load/store
 238         byte_reverse : std_ulogic;
 239         sign_extend : std_ulogic;                       -- do we need to sign extend?
 240         update : std_ulogic;                            -- is this an update instruction?
 241         update_reg : gpr_index_t;                       -- if so, the register to update
 242         xerc : xer_common_t;
 243         reserve : std_ulogic;                           -- set for larx/stcx.
 244         rc : std_ulogic;                                -- set for stcx.
 245         virt_mode : std_ulogic;                         -- do translation through TLB
 246         priv_mode : std_ulogic;                         -- privileged mode (MSR[PR] = 0)
 247     end record;
 248     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
 249                                                                      sign_extend => '0', update => '0', xerc => xerc_init,
 250                                                                      reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
 251                                                                      nia => (others => '0'), insn => (others => '0'),
 252                                                                      addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'), length => (others => '0'),
 253                                                                      others => (others => '0'));
 254
 255     type Loadstore1ToExecute1Type is record
 256         exception : std_ulogic;
 257         invalid : std_ulogic;
 258         perm_error : std_ulogic;
 259         rc_error : std_ulogic;
 260         badtree : std_ulogic;
 261         segment_fault : std_ulogic;
 262         instr_fault : std_ulogic;
 263     end record;
 264
 265     type Loadstore1ToDcacheType is record
 266         valid : std_ulogic;
 267         load : std_ulogic;                              -- is this a load
 268         dcbz : std_ulogic;
 269         nc : std_ulogic;
 270         reserve : std_ulogic;
 271         virt_mode : std_ulogic;
 272         priv_mode : std_ulogic;
 273         addr : std_ulogic_vector(63 downto 0);
 274         data : std_ulogic_vector(63 downto 0);
 275         byte_sel : std_ulogic_vector(7 downto 0);
 276     end record;
 277
 278     type DcacheToLoadstore1Type is record
 279         valid : std_ulogic;
 280         data : std_ulogic_vector(63 downto 0);
 281         store_done : std_ulogic;
 282         error : std_ulogic;
 283         cache_paradox : std_ulogic;
 284     end record;
 285
 286     type Loadstore1ToMmuType is record
 287         valid : std_ulogic;
 288         tlbie : std_ulogic;
 289         slbia : std_ulogic;
 290         mtspr : std_ulogic;
 291         iside : std_ulogic;
 292         load  : std_ulogic;
 293         priv  : std_ulogic;
 294         sprn  : std_ulogic_vector(9 downto 0);
 295         addr  : std_ulogic_vector(63 downto 0);
 296         rs    : std_ulogic_vector(63 downto 0);
 297     end record;
 298
 299     type MmuToLoadstore1Type is record
 300         done       : std_ulogic;
 301         invalid    : std_ulogic;
 302         badtree    : std_ulogic;
 303         segerr     : std_ulogic;
 304         perm_error : std_ulogic;
 305         rc_error   : std_ulogic;
 306         sprval     : std_ulogic_vector(63 downto 0);
 307     end record;
 308
 309     type MmuToDcacheType is record
 310         valid : std_ulogic;
 311         tlbie : std_ulogic;
 312         doall : std_ulogic;
 313         tlbld : std_ulogic;
 314         addr  : std_ulogic_vector(63 downto 0);
 315         pte   : std_ulogic_vector(63 downto 0);
 316     end record;
 317
 318     type DcacheToMmuType is record
 319         stall : std_ulogic;
 320         done  : std_ulogic;
 321         err   : std_ulogic;
 322         data  : std_ulogic_vector(63 downto 0);
 323     end record;
 324
 325     type MmuToIcacheType is record
 326         tlbld : std_ulogic;
 327         tlbie : std_ulogic;
 328         doall : std_ulogic;
 329         addr  : std_ulogic_vector(63 downto 0);
 330         pte   : std_ulogic_vector(63 downto 0);
 331     end record;
 332
 333     type Loadstore1ToWritebackType is record
 334         valid : std_ulogic;
 335         write_enable: std_ulogic;
 336         write_reg : gpr_index_t;
 337         write_data : std_ulogic_vector(63 downto 0);
 338         xerc : xer_common_t;
 339         rc : std_ulogic;
 340         store_done : std_ulogic;
 341     end record;
 342     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType := (valid => '0', write_enable => '0', xerc => xerc_init,
 343                                                                        rc => '0', store_done => '0', write_data => (others => '0'), others => (others => '0'));
 344
 345     type Execute1ToWritebackType is record
 346         valid: std_ulogic;
 347         rc : std_ulogic;
 348         write_enable : std_ulogic;
 349         write_reg: gspr_index_t;
 350         write_data: std_ulogic_vector(63 downto 0);
 351         write_cr_enable : std_ulogic;
 352         write_cr_mask : std_ulogic_vector(7 downto 0);
 353         write_cr_data : std_ulogic_vector(31 downto 0);
 354         write_xerc_enable : std_ulogic;
 355         xerc : xer_common_t;
 356         exc_write_enable : std_ulogic;
 357         exc_write_reg : gspr_index_t;
 358         exc_write_data : std_ulogic_vector(63 downto 0);
 359     end record;
 360     constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', write_enable => '0',
 361                                                                    write_cr_enable => '0', exc_write_enable => '0',
 362                                                                    write_xerc_enable => '0', xerc => xerc_init,
 363                                    write_data => (others => '0'), write_cr_mask => (others => '0'),
 364                                    write_cr_data => (others => '0'), write_reg => (others => '0'),
 365                                    exc_write_reg => (others => '0'), exc_write_data => (others => '0'));
 366
 367     type MultiplyToExecute1Type is record
 368         valid: std_ulogic;
 369         write_reg_data: std_ulogic_vector(63 downto 0);
 370         overflow : std_ulogic;
 371     end record;
 372     constant MultiplyToExecute1Init : MultiplyToExecute1Type := (valid => '0', overflow => '0',
 373                                                                  others => (others => '0'));
 374
 375     type DividerToExecute1Type is record
 376         valid: std_ulogic;
 377         write_reg_data: std_ulogic_vector(63 downto 0);
 378         overflow : std_ulogic;
 379     end record;
 380     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 381                                                                others => (others => '0'));
 382
 383     type WritebackToRegisterFileType is record
 384         write_reg : gspr_index_t;
 385         write_data : std_ulogic_vector(63 downto 0);
 386         write_enable : std_ulogic;
 387     end record;
 388     constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
 389
 390     type WritebackToCrFileType is record
 391         write_cr_enable : std_ulogic;
 392         write_cr_mask : std_ulogic_vector(7 downto 0);
 393         write_cr_data : std_ulogic_vector(31 downto 0);
 394         write_xerc_enable : std_ulogic;
 395         write_xerc_data : xer_common_t;
 396     end record;
 397     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 398                                                                write_xerc_data => xerc_init,
 399                                                                write_cr_mask => (others => '0'),
 400                                                                write_cr_data => (others => '0'));
 401
 402 end common;
 403
 404 package body common is
 405     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 406     begin
 407         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 408     end;
 409     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 410        variable n : integer range 0 to 31;
 411        -- tmp variable introduced as workaround for VCS compilation
 412        -- simulation was failing with subtype constraint mismatch error
 413        -- see GitHub PR #173
 414        variable tmp : std_ulogic_vector(4 downto 0);
 415     begin
 416        case spr is
 417        when SPR_LR =>
 418            n := 0;
 419        when SPR_CTR =>
 420            n:= 1;
 421        when SPR_SRR0 =>
 422            n := 2;
 423        when SPR_SRR1 =>
 424            n := 3;
 425        when SPR_HSRR0 =>
 426            n := 4;
 427        when SPR_HSRR1 =>
 428            n := 5;
 429        when SPR_SPRG0 =>
 430            n := 6;
 431        when SPR_SPRG1 =>
 432            n := 7;
 433        when SPR_SPRG2 =>
 434            n := 8;
 435        when SPR_SPRG3 | SPR_SPRG3U =>
 436            n := 9;
 437        when SPR_HSPRG0 =>
 438            n := 10;
 439        when SPR_HSPRG1 =>
 440            n := 11;
 441        when SPR_XER =>
 442            n := 12;
 443        when others =>
 444            n := 0;
 445            return "000000";
 446        end case;
 447        tmp := std_ulogic_vector(to_unsigned(n, 5));
 448        return "1" & tmp;
 449     end;
 450
 451     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 452     begin
 453         return i(4 downto 0);
 454     end;
 455
 456     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 457     begin
 458         return "0" & i;
 459     end;
 460
 461     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 462     begin
 463         if s(5) = '1' then
 464             return s;
 465         else
 466             return gpr_to_gspr(g);
 467         end if;
 468     end;
 469
 470     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 471     begin
 472         return s(5);
 473     end;
 474 end common;