2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 use work.decode_types.all;
10 -- Processor Version Number
11 constant PVR_MICROWATT : std_ulogic_vector(31 downto 0) := x"00630000";
14 constant MSR_SF : integer := (63 - 0); -- Sixty-Four bit mode
15 constant MSR_EE : integer := (63 - 48); -- External interrupt Enable
16 constant MSR_PR : integer := (63 - 49); -- PRoblem state
17 constant MSR_FP : integer := (63 - 50); -- Floating Point available
18 constant MSR_FE0 : integer := (63 - 52); -- Floating Exception mode
19 constant MSR_SE : integer := (63 - 53); -- Single-step bit of TE field
20 constant MSR_BE : integer := (63 - 54); -- Branch trace bit of TE field
21 constant MSR_FE1 : integer := (63 - 55); -- Floating Exception mode
22 constant MSR_IR : integer := (63 - 58); -- Instruction Relocation
23 constant MSR_DR : integer := (63 - 59); -- Data Relocation
24 constant MSR_RI : integer := (63 - 62); -- Recoverable Interrupt
25 constant MSR_LE : integer := (63 - 63); -- Little Endian
28 subtype spr_num_t is integer range 0 to 1023;
30 function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
32 constant SPR_XER : spr_num_t := 1;
33 constant SPR_LR : spr_num_t := 8;
34 constant SPR_CTR : spr_num_t := 9;
35 constant SPR_TAR : spr_num_t := 815;
36 constant SPR_DSISR : spr_num_t := 18;
37 constant SPR_DAR : spr_num_t := 19;
38 constant SPR_TB : spr_num_t := 268;
39 constant SPR_TBU : spr_num_t := 269;
40 constant SPR_DEC : spr_num_t := 22;
41 constant SPR_SRR0 : spr_num_t := 26;
42 constant SPR_SRR1 : spr_num_t := 27;
43 constant SPR_CFAR : spr_num_t := 28;
44 constant SPR_HSRR0 : spr_num_t := 314;
45 constant SPR_HSRR1 : spr_num_t := 315;
46 constant SPR_SPRG0 : spr_num_t := 272;
47 constant SPR_SPRG1 : spr_num_t := 273;
48 constant SPR_SPRG2 : spr_num_t := 274;
49 constant SPR_SPRG3 : spr_num_t := 275;
50 constant SPR_SPRG3U : spr_num_t := 259;
51 constant SPR_HSPRG0 : spr_num_t := 304;
52 constant SPR_HSPRG1 : spr_num_t := 305;
53 constant SPR_PID : spr_num_t := 48;
54 constant SPR_PRTBL : spr_num_t := 720;
55 constant SPR_PVR : spr_num_t := 287;
57 -- GPR indices in the register file (GPR only)
58 subtype gpr_index_t is std_ulogic_vector(4 downto 0);
60 -- Extended GPR index (can hold an SPR or a FPR)
61 subtype gspr_index_t is std_ulogic_vector(6 downto 0);
64 subtype fpr_index_t is std_ulogic_vector(4 downto 0);
66 -- Some SPRs are stored in the register file, they use the magic
67 -- GPR numbers above 31.
69 -- The function fast_spr_num() returns the corresponding fast
70 -- pseudo-GPR number for a given SPR number. The result MSB
71 -- indicates if this is indeed a fast SPR. If clear, then
72 -- the SPR is not stored in the GPR file.
74 -- FPRs are also stored in the register file, using GSPR
75 -- numbers from 64 to 95.
77 function fast_spr_num(spr: spr_num_t) return gspr_index_t;
79 -- Indices conversion functions
80 function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
81 function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
82 function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
83 function is_fast_spr(s: gspr_index_t) return std_ulogic;
84 function fpr_to_gspr(f: fpr_index_t) return gspr_index_t;
86 -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
87 -- in the CR file as a kind of CR extension (with a separate write
88 -- control). The rest is stored as a fast SPR.
89 type xer_common_t is record
96 constant xerc_init : xer_common_t := (others => '0');
99 constant FPSCR_FX : integer := 63 - 32;
100 constant FPSCR_FEX : integer := 63 - 33;
101 constant FPSCR_VX : integer := 63 - 34;
102 constant FPSCR_OX : integer := 63 - 35;
103 constant FPSCR_UX : integer := 63 - 36;
104 constant FPSCR_ZX : integer := 63 - 37;
105 constant FPSCR_XX : integer := 63 - 38;
106 constant FPSCR_VXSNAN : integer := 63 - 39;
107 constant FPSCR_VXISI : integer := 63 - 40;
108 constant FPSCR_VXIDI : integer := 63 - 41;
109 constant FPSCR_VXZDZ : integer := 63 - 42;
110 constant FPSCR_VXIMZ : integer := 63 - 43;
111 constant FPSCR_VXVC : integer := 63 - 44;
112 constant FPSCR_FR : integer := 63 - 45;
113 constant FPSCR_FI : integer := 63 - 46;
114 constant FPSCR_C : integer := 63 - 47;
115 constant FPSCR_FL : integer := 63 - 48;
116 constant FPSCR_FG : integer := 63 - 49;
117 constant FPSCR_FE : integer := 63 - 50;
118 constant FPSCR_FU : integer := 63 - 51;
119 constant FPSCR_VXSOFT : integer := 63 - 53;
120 constant FPSCR_VXSQRT : integer := 63 - 54;
121 constant FPSCR_VXCVI : integer := 63 - 55;
122 constant FPSCR_VE : integer := 63 - 56;
123 constant FPSCR_OE : integer := 63 - 57;
124 constant FPSCR_UE : integer := 63 - 58;
125 constant FPSCR_ZE : integer := 63 - 59;
126 constant FPSCR_XE : integer := 63 - 60;
127 constant FPSCR_NI : integer := 63 - 61;
128 constant FPSCR_RN : integer := 63 - 63;
130 -- Used for tracking instruction completion and pending register writes
131 constant TAG_COUNT : positive := 4;
132 constant TAG_NUMBER_BITS : natural := log2(TAG_COUNT);
133 subtype tag_number_t is integer range 0 to TAG_COUNT - 1;
134 subtype tag_index_t is unsigned(TAG_NUMBER_BITS - 1 downto 0);
135 type instr_tag_t is record
139 constant instr_tag_init : instr_tag_t := (tag => 0, valid => '0');
140 function tag_match(tag1 : instr_tag_t; tag2 : instr_tag_t) return boolean;
142 type irq_state_t is (WRITE_SRR0, WRITE_SRR1);
144 -- For now, fixed 16 sources, make this either a parametric
145 -- package of some sort or an unconstrainted array.
146 type ics_to_icp_t is record
147 -- Level interrupts only, ICS just keeps prsenting the
148 -- highest priority interrupt. Once handling edge, something
149 -- smarter involving handshake & reject support will be needed
150 src : std_ulogic_vector(3 downto 0);
151 pri : std_ulogic_vector(7 downto 0);
154 -- This needs to die...
155 type ctrl_t is record
156 tb: std_ulogic_vector(63 downto 0);
157 dec: std_ulogic_vector(63 downto 0);
158 msr: std_ulogic_vector(63 downto 0);
159 cfar: std_ulogic_vector(63 downto 0);
160 irq_state : irq_state_t;
161 srr1: std_ulogic_vector(63 downto 0);
164 type Fetch1ToIcacheType is record
166 virt_mode : std_ulogic;
167 priv_mode : std_ulogic;
168 big_endian : std_ulogic;
169 stop_mark: std_ulogic;
170 sequential: std_ulogic;
171 predicted : std_ulogic;
172 nia: std_ulogic_vector(63 downto 0);
175 type IcacheToDecode1Type is record
177 stop_mark: std_ulogic;
178 fetch_failed: std_ulogic;
179 nia: std_ulogic_vector(63 downto 0);
180 insn: std_ulogic_vector(31 downto 0);
181 big_endian: std_ulogic;
182 next_predicted: std_ulogic;
185 type Decode1ToDecode2Type is record
187 stop_mark : std_ulogic;
188 nia: std_ulogic_vector(63 downto 0);
189 insn: std_ulogic_vector(31 downto 0);
190 ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
191 ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
192 ispro: gspr_index_t; -- (G)SPR written with LR or CTR
193 decode: decode_rom_t;
194 br_pred: std_ulogic; -- Branch was predicted to be taken
195 big_endian: std_ulogic;
197 constant Decode1ToDecode2Init : Decode1ToDecode2Type :=
198 (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'),
199 ispr1 => (others => '0'), ispr2 => (others => '0'), ispro => (others => '0'),
200 decode => decode_rom_init, br_pred => '0', big_endian => '0');
202 type Decode1ToFetch1Type is record
203 redirect : std_ulogic;
204 redirect_nia : std_ulogic_vector(63 downto 0);
207 type bypass_data_t is record
209 data : std_ulogic_vector(63 downto 0);
211 constant bypass_data_init : bypass_data_t := (tag => instr_tag_init, data => (others => '0'));
213 type cr_bypass_data_t is record
215 data : std_ulogic_vector(31 downto 0);
217 constant cr_bypass_data_init : cr_bypass_data_t := (tag => instr_tag_init, data => (others => '0'));
219 type Decode2ToExecute1Type is record
223 insn_type: insn_type_t;
224 nia: std_ulogic_vector(63 downto 0);
225 instr_tag : instr_tag_t;
226 write_reg: gspr_index_t;
227 write_reg_enable: std_ulogic;
228 read_reg1: gspr_index_t;
229 read_reg2: gspr_index_t;
230 read_data1: std_ulogic_vector(63 downto 0);
231 read_data2: std_ulogic_vector(63 downto 0);
232 read_data3: std_ulogic_vector(63 downto 0);
233 cr: std_ulogic_vector(31 downto 0);
239 invert_a: std_ulogic;
241 invert_out: std_ulogic;
242 input_carry: carry_in_t;
243 output_carry: std_ulogic;
244 input_cr: std_ulogic;
245 output_cr: std_ulogic;
246 is_32bit: std_ulogic;
247 is_signed: std_ulogic;
248 insn: std_ulogic_vector(31 downto 0);
249 data_len: std_ulogic_vector(3 downto 0);
250 byte_reverse : std_ulogic;
251 sign_extend : std_ulogic; -- do we need to sign extend?
252 update : std_ulogic; -- is this an update instruction?
253 reserve : std_ulogic; -- set for larx/stcx
254 br_pred : std_ulogic;
255 result_sel : std_ulogic_vector(2 downto 0); -- select source of result
256 sub_select : std_ulogic_vector(2 downto 0); -- sub-result selection
257 repeat : std_ulogic; -- set if instruction is cracked into two ops
258 second : std_ulogic; -- set if this is the second op
260 constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
261 (valid => '0', unit => NONE, fac => NONE, insn_type => OP_ILLEGAL, instr_tag => instr_tag_init,
262 write_reg_enable => '0',
263 lr => '0', br_abs => '0', rc => '0', oe => '0', invert_a => '0', addm1 => '0',
264 invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
265 is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0', br_pred => '0',
266 byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'),
267 read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'),
268 cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'),
269 result_sel => "000", sub_select => "000",
270 repeat => '0', second => '0', others => (others => '0'));
272 type MultiplyInputType is record
274 data1: std_ulogic_vector(63 downto 0);
275 data2: std_ulogic_vector(63 downto 0);
276 addend: std_ulogic_vector(127 downto 0);
277 is_32bit: std_ulogic;
278 not_result: std_ulogic;
280 constant MultiplyInputInit : MultiplyInputType := (valid => '0',
281 is_32bit => '0', not_result => '0',
282 others => (others => '0'));
284 type MultiplyOutputType is record
286 result: std_ulogic_vector(127 downto 0);
287 overflow : std_ulogic;
289 constant MultiplyOutputInit : MultiplyOutputType := (valid => '0', overflow => '0',
290 others => (others => '0'));
292 type Execute1ToDividerType is record
294 dividend: std_ulogic_vector(63 downto 0);
295 divisor: std_ulogic_vector(63 downto 0);
296 is_signed: std_ulogic;
297 is_32bit: std_ulogic;
298 is_extended: std_ulogic;
299 is_modulus: std_ulogic;
300 neg_result: std_ulogic;
302 constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
303 is_extended => '0', is_modulus => '0',
304 neg_result => '0', others => (others => '0'));
306 type Decode2ToRegisterFileType is record
307 read1_enable : std_ulogic;
308 read1_reg : gspr_index_t;
309 read2_enable : std_ulogic;
310 read2_reg : gspr_index_t;
311 read3_enable : std_ulogic;
312 read3_reg : gspr_index_t;
315 type RegisterFileToDecode2Type is record
316 read1_data : std_ulogic_vector(63 downto 0);
317 read2_data : std_ulogic_vector(63 downto 0);
318 read3_data : std_ulogic_vector(63 downto 0);
321 type Decode2ToCrFileType is record
325 type CrFileToDecode2Type is record
326 read_cr_data : std_ulogic_vector(31 downto 0);
327 read_xerc_data : xer_common_t;
330 type Execute1ToFetch1Type is record
331 redirect: std_ulogic;
332 virt_mode: std_ulogic;
333 priv_mode: std_ulogic;
334 big_endian: std_ulogic;
335 mode_32bit: std_ulogic;
336 redirect_nia: std_ulogic_vector(63 downto 0);
337 br_nia : std_ulogic_vector(63 downto 0);
338 br_last : std_ulogic;
339 br_taken : std_ulogic;
341 constant Execute1ToFetch1Init : Execute1ToFetch1Type := (redirect => '0', virt_mode => '0',
342 priv_mode => '0', big_endian => '0',
343 mode_32bit => '0', br_taken => '0',
344 br_last => '0', others => (others => '0'));
346 type Execute1ToLoadstore1Type is record
348 op : insn_type_t; -- what ld/st or m[tf]spr or TLB op to do
349 nia : std_ulogic_vector(63 downto 0);
350 insn : std_ulogic_vector(31 downto 0);
351 instr_tag : instr_tag_t;
352 addr1 : std_ulogic_vector(63 downto 0);
353 addr2 : std_ulogic_vector(63 downto 0);
354 data : std_ulogic_vector(63 downto 0); -- data to write, unused for read
355 write_reg : gspr_index_t;
356 length : std_ulogic_vector(3 downto 0);
357 ci : std_ulogic; -- cache-inhibited load/store
358 byte_reverse : std_ulogic;
359 sign_extend : std_ulogic; -- do we need to sign extend?
360 update : std_ulogic; -- is this an update instruction?
362 reserve : std_ulogic; -- set for larx/stcx.
363 rc : std_ulogic; -- set for stcx.
364 virt_mode : std_ulogic; -- do translation through TLB
365 priv_mode : std_ulogic; -- privileged mode (MSR[PR] = 0)
366 mode_32bit : std_ulogic; -- trim addresses to 32 bits
367 is_32bit : std_ulogic;
371 constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type :=
372 (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
373 sign_extend => '0', update => '0', xerc => xerc_init,
374 reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
375 nia => (others => '0'), insn => (others => '0'),
376 instr_tag => instr_tag_init,
377 addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'),
378 write_reg => (others => '0'),
379 length => (others => '0'),
380 mode_32bit => '0', is_32bit => '0',
381 repeat => '0', second => '0');
383 type Loadstore1ToExecute1Type is record
385 exception : std_ulogic;
386 alignment : std_ulogic;
387 invalid : std_ulogic;
388 perm_error : std_ulogic;
389 rc_error : std_ulogic;
390 badtree : std_ulogic;
391 segment_fault : std_ulogic;
392 instr_fault : std_ulogic;
395 type Loadstore1ToDcacheType is record
397 load : std_ulogic; -- is this a load
400 reserve : std_ulogic;
401 atomic : std_ulogic; -- part of a multi-transfer atomic op
402 atomic_last : std_ulogic;
403 virt_mode : std_ulogic;
404 priv_mode : std_ulogic;
405 addr : std_ulogic_vector(63 downto 0);
406 data : std_ulogic_vector(63 downto 0); -- valid the cycle after .valid = 1
407 byte_sel : std_ulogic_vector(7 downto 0);
410 type DcacheToLoadstore1Type is record
412 data : std_ulogic_vector(63 downto 0);
413 store_done : std_ulogic;
415 cache_paradox : std_ulogic;
418 type Loadstore1ToMmuType is record
426 sprn : std_ulogic_vector(9 downto 0);
427 addr : std_ulogic_vector(63 downto 0);
428 rs : std_ulogic_vector(63 downto 0);
431 type MmuToLoadstore1Type is record
434 invalid : std_ulogic;
435 badtree : std_ulogic;
437 perm_error : std_ulogic;
438 rc_error : std_ulogic;
439 sprval : std_ulogic_vector(63 downto 0);
442 type MmuToDcacheType is record
447 addr : std_ulogic_vector(63 downto 0);
448 pte : std_ulogic_vector(63 downto 0);
451 type DcacheToMmuType is record
455 data : std_ulogic_vector(63 downto 0);
458 type MmuToIcacheType is record
462 addr : std_ulogic_vector(63 downto 0);
463 pte : std_ulogic_vector(63 downto 0);
466 type Loadstore1ToWritebackType is record
468 instr_tag : instr_tag_t;
469 write_enable: std_ulogic;
470 write_reg : gspr_index_t;
471 write_data : std_ulogic_vector(63 downto 0);
474 store_done : std_ulogic;
476 constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType :=
477 (valid => '0', instr_tag => instr_tag_init, write_enable => '0', xerc => xerc_init,
478 rc => '0', store_done => '0', write_data => (others => '0'), others => (others => '0'));
480 type Execute1ToWritebackType is record
482 instr_tag : instr_tag_t;
484 mode_32bit : std_ulogic;
485 write_enable : std_ulogic;
486 write_reg: gspr_index_t;
487 write_data: std_ulogic_vector(63 downto 0);
488 write_cr_enable : std_ulogic;
489 write_cr_mask : std_ulogic_vector(7 downto 0);
490 write_cr_data : std_ulogic_vector(31 downto 0);
491 write_xerc_enable : std_ulogic;
493 exc_write_enable : std_ulogic;
494 exc_write_reg : gspr_index_t;
495 exc_write_data : std_ulogic_vector(63 downto 0);
497 constant Execute1ToWritebackInit : Execute1ToWritebackType :=
498 (valid => '0', instr_tag => instr_tag_init, rc => '0', mode_32bit => '0',
499 write_enable => '0', write_cr_enable => '0', exc_write_enable => '0',
500 write_xerc_enable => '0', xerc => xerc_init,
501 write_data => (others => '0'), write_cr_mask => (others => '0'),
502 write_cr_data => (others => '0'), write_reg => (others => '0'),
503 exc_write_reg => (others => '0'), exc_write_data => (others => '0'));
505 type Execute1ToFPUType is record
508 nia : std_ulogic_vector(63 downto 0);
510 insn : std_ulogic_vector(31 downto 0);
512 fe_mode : std_ulogic_vector(1 downto 0);
513 fra : std_ulogic_vector(63 downto 0);
514 frb : std_ulogic_vector(63 downto 0);
515 frc : std_ulogic_vector(63 downto 0);
520 constant Execute1ToFPUInit : Execute1ToFPUType := (valid => '0', op => OP_ILLEGAL, nia => (others => '0'),
521 itag => instr_tag_init,
522 insn => (others => '0'), fe_mode => "00", rc => '0',
523 fra => (others => '0'), frb => (others => '0'),
524 frc => (others => '0'), frt => (others => '0'),
525 single => '0', out_cr => '0');
527 type FPUToExecute1Type is record
529 exception : std_ulogic;
530 interrupt : std_ulogic;
531 illegal : std_ulogic;
533 constant FPUToExecute1Init : FPUToExecute1Type := (others => '0');
535 type FPUToWritebackType is record
537 instr_tag : instr_tag_t;
538 write_enable : std_ulogic;
539 write_reg : gspr_index_t;
540 write_data : std_ulogic_vector(63 downto 0);
541 write_cr_enable : std_ulogic;
542 write_cr_mask : std_ulogic_vector(7 downto 0);
543 write_cr_data : std_ulogic_vector(31 downto 0);
545 constant FPUToWritebackInit : FPUToWritebackType := (valid => '0', instr_tag => instr_tag_init,
546 write_enable => '0', write_cr_enable => '0',
547 others => (others => '0'));
549 type DividerToExecute1Type is record
551 write_reg_data: std_ulogic_vector(63 downto 0);
552 overflow : std_ulogic;
554 constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
555 others => (others => '0'));
557 type WritebackToRegisterFileType is record
558 write_reg : gspr_index_t;
559 write_data : std_ulogic_vector(63 downto 0);
560 write_enable : std_ulogic;
562 constant WritebackToRegisterFileInit : WritebackToRegisterFileType :=
563 (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
565 type WritebackToCrFileType is record
566 write_cr_enable : std_ulogic;
567 write_cr_mask : std_ulogic_vector(7 downto 0);
568 write_cr_data : std_ulogic_vector(31 downto 0);
569 write_xerc_enable : std_ulogic;
570 write_xerc_data : xer_common_t;
572 constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
573 write_xerc_data => xerc_init,
574 write_cr_mask => (others => '0'),
575 write_cr_data => (others => '0'));
579 package body common is
580 function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
582 return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
584 function fast_spr_num(spr: spr_num_t) return gspr_index_t is
585 variable n : integer range 0 to 31;
586 -- tmp variable introduced as workaround for VCS compilation
587 -- simulation was failing with subtype constraint mismatch error
588 -- see GitHub PR #173
589 variable tmp : std_ulogic_vector(4 downto 0);
593 n := 0; -- N.B. decode2 relies on this specific value
595 n := 1; -- N.B. decode2 relies on this specific value
610 when SPR_SPRG3 | SPR_SPRG3U =>
624 tmp := std_ulogic_vector(to_unsigned(n, 5));
628 function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
630 return i(4 downto 0);
633 function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
638 function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
643 return gpr_to_gspr(g);
647 function is_fast_spr(s: gspr_index_t) return std_ulogic is
652 function fpr_to_gspr(f: fpr_index_t) return gspr_index_t is
657 function tag_match(tag1 : instr_tag_t; tag2 : instr_tag_t) return boolean is
659 return tag1.valid = '1' and tag2.valid = '1' and tag1.tag = tag2.tag;