common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7
   8 package common is
   9
  10     -- MSR bit numbers
  11     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  12     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  13     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  14     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  15     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  16     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  17     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  18
  19     -- SPR numbers
  20     subtype spr_num_t is integer range 0 to 1023;
  21
  22     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  23
  24     constant SPR_XER    : spr_num_t := 1;
  25     constant SPR_LR     : spr_num_t := 8;
  26     constant SPR_CTR    : spr_num_t := 9;
  27     constant SPR_DSISR  : spr_num_t := 18;
  28     constant SPR_DAR    : spr_num_t := 19;
  29     constant SPR_TB     : spr_num_t := 268;
  30     constant SPR_DEC    : spr_num_t := 22;
  31     constant SPR_SRR0   : spr_num_t := 26;
  32     constant SPR_SRR1   : spr_num_t := 27;
  33     constant SPR_HSRR0  : spr_num_t := 314;
  34     constant SPR_HSRR1  : spr_num_t := 315;
  35     constant SPR_SPRG0  : spr_num_t := 272;
  36     constant SPR_SPRG1  : spr_num_t := 273;
  37     constant SPR_SPRG2  : spr_num_t := 274;
  38     constant SPR_SPRG3  : spr_num_t := 275;
  39     constant SPR_SPRG3U : spr_num_t := 259;
  40     constant SPR_HSPRG0 : spr_num_t := 304;
  41     constant SPR_HSPRG1 : spr_num_t := 305;
  42     constant SPR_PID    : spr_num_t := 48;
  43     constant SPR_PRTBL  : spr_num_t := 720;
  44
  45     -- GPR indices in the register file (GPR only)
  46     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  47
  48     -- Extended GPR indice (can hold an SPR)
  49     subtype gspr_index_t is std_ulogic_vector(5 downto 0);
  50
  51     -- Some SPRs are stored in the register file, they use the magic
  52     -- GPR numbers above 31.
  53     --
  54     -- The function fast_spr_num() returns the corresponding fast
  55     -- pseudo-GPR number for a given SPR number. The result MSB
  56     -- indicates if this is indeed a fast SPR. If clear, then
  57     -- the SPR is not stored in the GPR file.
  58     --
  59     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
  60
  61     -- Indices conversion functions
  62     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
  63     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
  64     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
  65     function is_fast_spr(s: gspr_index_t) return std_ulogic;
  66
  67     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
  68     -- in the CR file as a kind of CR extension (with a separate write
  69     -- control). The rest is stored as a fast SPR.
  70     type xer_common_t is record
  71         ca : std_ulogic;
  72         ca32 : std_ulogic;
  73         ov : std_ulogic;
  74         ov32 : std_ulogic;
  75         so : std_ulogic;
  76     end record;
  77     constant xerc_init : xer_common_t := (others => '0');
  78
  79     type irq_state_t is (WRITE_SRR0, WRITE_SRR1);
  80
  81     -- This needs to die...
  82     type ctrl_t is record
  83         tb: std_ulogic_vector(63 downto 0);
  84         dec: std_ulogic_vector(63 downto 0);
  85         msr: std_ulogic_vector(63 downto 0);
  86         irq_state : irq_state_t;
  87         irq_nia: std_ulogic_vector(63 downto 0);
  88         srr1: std_ulogic_vector(63 downto 0);
  89     end record;
  90
  91     type Fetch1ToIcacheType is record
  92         req: std_ulogic;
  93         virt_mode : std_ulogic;
  94         priv_mode : std_ulogic;
  95         stop_mark: std_ulogic;
  96         nia: std_ulogic_vector(63 downto 0);
  97     end record;
  98
  99     type IcacheToFetch2Type is record
 100         valid: std_ulogic;
 101         stop_mark: std_ulogic;
 102         fetch_failed: std_ulogic;
 103         nia: std_ulogic_vector(63 downto 0);
 104         insn: std_ulogic_vector(31 downto 0);
 105     end record;
 106
 107     type Fetch2ToDecode1Type is record
 108         valid: std_ulogic;
 109         stop_mark : std_ulogic;
 110         fetch_failed: std_ulogic;
 111         nia: std_ulogic_vector(63 downto 0);
 112         insn: std_ulogic_vector(31 downto 0);
 113     end record;
 114     constant Fetch2ToDecode1Init : Fetch2ToDecode1Type := (valid => '0', stop_mark => '0', fetch_failed => '0',
 115                                                            others => (others => '0'));
 116
 117     type Decode1ToDecode2Type is record
 118         valid: std_ulogic;
 119         stop_mark : std_ulogic;
 120         nia: std_ulogic_vector(63 downto 0);
 121         insn: std_ulogic_vector(31 downto 0);
 122         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
 123         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
 124         decode: decode_rom_t;
 125     end record;
 126     constant Decode1ToDecode2Init : Decode1ToDecode2Type := (valid => '0', stop_mark => '0', decode => decode_rom_init, others => (others => '0'));
 127
 128     type Decode2ToExecute1Type is record
 129         valid: std_ulogic;
 130         unit : unit_t;
 131         insn_type: insn_type_t;
 132         nia: std_ulogic_vector(63 downto 0);
 133         write_reg: gspr_index_t;
 134         read_reg1: gspr_index_t;
 135         read_reg2: gspr_index_t;
 136         read_data1: std_ulogic_vector(63 downto 0);
 137         read_data2: std_ulogic_vector(63 downto 0);
 138         read_data3: std_ulogic_vector(63 downto 0);
 139         bypass_data1: std_ulogic;
 140         bypass_data2: std_ulogic;
 141         bypass_data3: std_ulogic;
 142         cr: std_ulogic_vector(31 downto 0);
 143         xerc: xer_common_t;
 144         lr: std_ulogic;
 145         rc: std_ulogic;
 146         oe: std_ulogic;
 147         invert_a: std_ulogic;
 148         invert_out: std_ulogic;
 149         input_carry: carry_in_t;
 150         output_carry: std_ulogic;
 151         input_cr: std_ulogic;
 152         output_cr: std_ulogic;
 153         is_32bit: std_ulogic;
 154         is_signed: std_ulogic;
 155         insn: std_ulogic_vector(31 downto 0);
 156         data_len: std_ulogic_vector(3 downto 0);
 157         byte_reverse : std_ulogic;
 158         sign_extend : std_ulogic;                       -- do we need to sign extend?
 159         update : std_ulogic;                            -- is this an update instruction?
 160         reserve : std_ulogic;                           -- set for larx/stcx
 161     end record;
 162     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 163         (valid => '0', unit => NONE, insn_type => OP_ILLEGAL, bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
 164          lr => '0', rc => '0', oe => '0', invert_a => '0',
 165          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
 166          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0',
 167          byte_reverse => '0', sign_extend => '0', update => '0', others => (others => '0'));
 168
 169     type Execute1ToMultiplyType is record
 170         valid: std_ulogic;
 171         insn_type: insn_type_t;
 172         data1: std_ulogic_vector(64 downto 0);
 173         data2: std_ulogic_vector(64 downto 0);
 174         is_32bit: std_ulogic;
 175     end record;
 176     constant Execute1ToMultiplyInit : Execute1ToMultiplyType := (valid => '0', insn_type => OP_ILLEGAL,
 177                                                                  is_32bit => '0',
 178                                                                  others => (others => '0'));
 179
 180     type Execute1ToDividerType is record
 181         valid: std_ulogic;
 182         dividend: std_ulogic_vector(63 downto 0);
 183         divisor: std_ulogic_vector(63 downto 0);
 184         is_signed: std_ulogic;
 185         is_32bit: std_ulogic;
 186         is_extended: std_ulogic;
 187         is_modulus: std_ulogic;
 188         neg_result: std_ulogic;
 189     end record;
 190     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 191                                                               is_extended => '0', is_modulus => '0',
 192                                                               neg_result => '0', others => (others => '0'));
 193
 194     type Decode2ToRegisterFileType is record
 195         read1_enable : std_ulogic;
 196         read1_reg : gspr_index_t;
 197         read2_enable : std_ulogic;
 198         read2_reg : gspr_index_t;
 199         read3_enable : std_ulogic;
 200         read3_reg : gpr_index_t;
 201     end record;
 202
 203     type RegisterFileToDecode2Type is record
 204         read1_data : std_ulogic_vector(63 downto 0);
 205         read2_data : std_ulogic_vector(63 downto 0);
 206         read3_data : std_ulogic_vector(63 downto 0);
 207     end record;
 208
 209     type Decode2ToCrFileType is record
 210         read : std_ulogic;
 211     end record;
 212
 213     type CrFileToDecode2Type is record
 214         read_cr_data   : std_ulogic_vector(31 downto 0);
 215         read_xerc_data : xer_common_t;
 216     end record;
 217
 218     type Execute1ToFetch1Type is record
 219         redirect: std_ulogic;
 220         virt_mode: std_ulogic;
 221         priv_mode: std_ulogic;
 222         redirect_nia: std_ulogic_vector(63 downto 0);
 223     end record;
 224     constant Execute1ToFetch1TypeInit : Execute1ToFetch1Type := (redirect => '0', virt_mode => '0',
 225                                                                  priv_mode => '0', others => (others => '0'));
 226
 227     type Execute1ToLoadstore1Type is record
 228         valid : std_ulogic;
 229         op : insn_type_t;                               -- what ld/st or m[tf]spr or TLB op to do
 230         nia : std_ulogic_vector(63 downto 0);
 231         insn : std_ulogic_vector(31 downto 0);
 232         addr1 : std_ulogic_vector(63 downto 0);
 233         addr2 : std_ulogic_vector(63 downto 0);
 234         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 235         write_reg : gpr_index_t;
 236         length : std_ulogic_vector(3 downto 0);
 237         ci : std_ulogic;                                -- cache-inhibited load/store
 238         byte_reverse : std_ulogic;
 239         sign_extend : std_ulogic;                       -- do we need to sign extend?
 240         update : std_ulogic;                            -- is this an update instruction?
 241         update_reg : gpr_index_t;                       -- if so, the register to update
 242         xerc : xer_common_t;
 243         reserve : std_ulogic;                           -- set for larx/stcx.
 244         rc : std_ulogic;                                -- set for stcx.
 245         virt_mode : std_ulogic;                         -- do translation through TLB
 246         priv_mode : std_ulogic;                         -- privileged mode (MSR[PR] = 0)
 247     end record;
 248     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
 249                                                                      sign_extend => '0', update => '0', xerc => xerc_init,
 250                                                                      reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
 251                                                                      others => (others => '0'));
 252
 253     type Loadstore1ToExecute1Type is record
 254         exception : std_ulogic;
 255         invalid : std_ulogic;
 256         perm_error : std_ulogic;
 257         rc_error : std_ulogic;
 258         badtree : std_ulogic;
 259         segment_fault : std_ulogic;
 260         instr_fault : std_ulogic;
 261     end record;
 262
 263     type Loadstore1ToDcacheType is record
 264         valid : std_ulogic;
 265         load : std_ulogic;                              -- is this a load
 266         dcbz : std_ulogic;
 267         nc : std_ulogic;
 268         reserve : std_ulogic;
 269         virt_mode : std_ulogic;
 270         priv_mode : std_ulogic;
 271         addr : std_ulogic_vector(63 downto 0);
 272         data : std_ulogic_vector(63 downto 0);
 273         byte_sel : std_ulogic_vector(7 downto 0);
 274     end record;
 275
 276     type DcacheToLoadstore1Type is record
 277         valid : std_ulogic;
 278         data : std_ulogic_vector(63 downto 0);
 279         store_done : std_ulogic;
 280         error : std_ulogic;
 281         cache_paradox : std_ulogic;
 282     end record;
 283
 284     type Loadstore1ToMmuType is record
 285         valid : std_ulogic;
 286         tlbie : std_ulogic;
 287         slbia : std_ulogic;
 288         mtspr : std_ulogic;
 289         iside : std_ulogic;
 290         load  : std_ulogic;
 291         priv  : std_ulogic;
 292         sprn  : std_ulogic_vector(9 downto 0);
 293         addr  : std_ulogic_vector(63 downto 0);
 294         rs    : std_ulogic_vector(63 downto 0);
 295     end record;
 296
 297     type MmuToLoadstore1Type is record
 298         done       : std_ulogic;
 299         invalid    : std_ulogic;
 300         badtree    : std_ulogic;
 301         segerr     : std_ulogic;
 302         perm_error : std_ulogic;
 303         rc_error   : std_ulogic;
 304         sprval     : std_ulogic_vector(63 downto 0);
 305     end record;
 306
 307     type MmuToDcacheType is record
 308         valid : std_ulogic;
 309         tlbie : std_ulogic;
 310         doall : std_ulogic;
 311         tlbld : std_ulogic;
 312         addr  : std_ulogic_vector(63 downto 0);
 313         pte   : std_ulogic_vector(63 downto 0);
 314     end record;
 315
 316     type DcacheToMmuType is record
 317         stall : std_ulogic;
 318         done  : std_ulogic;
 319         err   : std_ulogic;
 320         data  : std_ulogic_vector(63 downto 0);
 321     end record;
 322
 323     type MmuToIcacheType is record
 324         tlbld : std_ulogic;
 325         tlbie : std_ulogic;
 326         doall : std_ulogic;
 327         addr  : std_ulogic_vector(63 downto 0);
 328         pte   : std_ulogic_vector(63 downto 0);
 329     end record;
 330
 331     type Loadstore1ToWritebackType is record
 332         valid : std_ulogic;
 333         write_enable: std_ulogic;
 334         write_reg : gpr_index_t;
 335         write_data : std_ulogic_vector(63 downto 0);
 336         xerc : xer_common_t;
 337         rc : std_ulogic;
 338         store_done : std_ulogic;
 339     end record;
 340     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType := (valid => '0', write_enable => '0', xerc => xerc_init,
 341                                                                        rc => '0', store_done => '0', others => (others => '0'));
 342
 343     type Execute1ToWritebackType is record
 344         valid: std_ulogic;
 345         rc : std_ulogic;
 346         write_enable : std_ulogic;
 347         write_reg: gspr_index_t;
 348         write_data: std_ulogic_vector(63 downto 0);
 349         write_cr_enable : std_ulogic;
 350         write_cr_mask : std_ulogic_vector(7 downto 0);
 351         write_cr_data : std_ulogic_vector(31 downto 0);
 352         write_xerc_enable : std_ulogic;
 353         xerc : xer_common_t;
 354         exc_write_enable : std_ulogic;
 355         exc_write_reg : gspr_index_t;
 356         exc_write_data : std_ulogic_vector(63 downto 0);
 357     end record;
 358     constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', write_enable => '0',
 359                                                                    write_cr_enable => '0', exc_write_enable => '0',
 360                                                                    write_xerc_enable => '0', xerc => xerc_init,
 361                                                                    others => (others => '0'));
 362
 363     type MultiplyToExecute1Type is record
 364         valid: std_ulogic;
 365         write_reg_data: std_ulogic_vector(63 downto 0);
 366         overflow : std_ulogic;
 367     end record;
 368     constant MultiplyToExecute1Init : MultiplyToExecute1Type := (valid => '0', overflow => '0',
 369                                                                  others => (others => '0'));
 370
 371     type DividerToExecute1Type is record
 372         valid: std_ulogic;
 373         write_reg_data: std_ulogic_vector(63 downto 0);
 374         overflow : std_ulogic;
 375     end record;
 376     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 377                                                                others => (others => '0'));
 378
 379     type WritebackToRegisterFileType is record
 380         write_reg : gspr_index_t;
 381         write_data : std_ulogic_vector(63 downto 0);
 382         write_enable : std_ulogic;
 383     end record;
 384     constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', others => (others => '0'));
 385
 386     type WritebackToCrFileType is record
 387         write_cr_enable : std_ulogic;
 388         write_cr_mask : std_ulogic_vector(7 downto 0);
 389         write_cr_data : std_ulogic_vector(31 downto 0);
 390         write_xerc_enable : std_ulogic;
 391         write_xerc_data : xer_common_t;
 392     end record;
 393     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 394                                                                write_xerc_data => xerc_init,
 395                                                                others => (others => '0'));
 396
 397     type XicsToExecute1Type is record
 398         irq : std_ulogic;
 399     end record;
 400
 401 end common;
 402
 403 package body common is
 404     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 405     begin
 406         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 407     end;
 408     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 409        variable n : integer range 0 to 31;
 410     begin
 411        case spr is
 412        when SPR_LR =>
 413            n := 0;
 414        when SPR_CTR =>
 415            n:= 1;
 416        when SPR_SRR0 =>
 417            n := 2;
 418        when SPR_SRR1 =>
 419            n := 3;
 420        when SPR_HSRR0 =>
 421            n := 4;
 422        when SPR_HSRR1 =>
 423            n := 5;
 424        when SPR_SPRG0 =>
 425            n := 6;
 426        when SPR_SPRG1 =>
 427            n := 7;
 428        when SPR_SPRG2 =>
 429            n := 8;
 430        when SPR_SPRG3 | SPR_SPRG3U =>
 431            n := 9;
 432        when SPR_HSPRG0 =>
 433            n := 10;
 434        when SPR_HSPRG1 =>
 435            n := 11;
 436        when SPR_XER =>
 437            n := 12;
 438        when others =>
 439            n := 0;
 440            return "000000";
 441        end case;
 442        return "1" & std_ulogic_vector(to_unsigned(n, 5));
 443     end;
 444
 445     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 446     begin
 447         return i(4 downto 0);
 448     end;
 449
 450     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 451     begin
 452         return "0" & i;
 453     end;
 454
 455     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 456     begin
 457         if s(5) = '1' then
 458             return s;
 459         else
 460             return gpr_to_gspr(g);
 461         end if;
 462     end;
 463
 464     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 465     begin
 466         return s(5);
 467     end;
 468 end common;