common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7
   8 package common is
   9
  10     -- MSR bit numbers
  11     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  12     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  13     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  14     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  15     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  16     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  17     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  18
  19     -- SPR numbers
  20     subtype spr_num_t is integer range 0 to 1023;
  21
  22     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  23
  24     constant SPR_XER    : spr_num_t := 1;
  25     constant SPR_LR     : spr_num_t := 8;
  26     constant SPR_CTR    : spr_num_t := 9;
  27     constant SPR_DSISR  : spr_num_t := 18;
  28     constant SPR_DAR    : spr_num_t := 19;
  29     constant SPR_TB     : spr_num_t := 268;
  30     constant SPR_DEC    : spr_num_t := 22;
  31     constant SPR_SRR0   : spr_num_t := 26;
  32     constant SPR_SRR1   : spr_num_t := 27;
  33     constant SPR_HSRR0  : spr_num_t := 314;
  34     constant SPR_HSRR1  : spr_num_t := 315;
  35     constant SPR_SPRG0  : spr_num_t := 272;
  36     constant SPR_SPRG1  : spr_num_t := 273;
  37     constant SPR_SPRG2  : spr_num_t := 274;
  38     constant SPR_SPRG3  : spr_num_t := 275;
  39     constant SPR_SPRG3U : spr_num_t := 259;
  40     constant SPR_HSPRG0 : spr_num_t := 304;
  41     constant SPR_HSPRG1 : spr_num_t := 305;
  42
  43     -- GPR indices in the register file (GPR only)
  44     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  45
  46     -- Extended GPR indice (can hold an SPR)
  47     subtype gspr_index_t is std_ulogic_vector(5 downto 0);
  48
  49     -- Some SPRs are stored in the register file, they use the magic
  50     -- GPR numbers above 31.
  51     --
  52     -- The function fast_spr_num() returns the corresponding fast
  53     -- pseudo-GPR number for a given SPR number. The result MSB
  54     -- indicates if this is indeed a fast SPR. If clear, then
  55     -- the SPR is not stored in the GPR file.
  56     --
  57     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
  58
  59     -- Indices conversion functions
  60     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
  61     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
  62     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
  63     function is_fast_spr(s: gspr_index_t) return std_ulogic;
  64
  65     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
  66     -- in the CR file as a kind of CR extension (with a separate write
  67     -- control). The rest is stored as a fast SPR.
  68     type xer_common_t is record
  69         ca : std_ulogic;
  70         ca32 : std_ulogic;
  71         ov : std_ulogic;
  72         ov32 : std_ulogic;
  73         so : std_ulogic;
  74     end record;
  75     constant xerc_init : xer_common_t := (others => '0');
  76
  77     type irq_state_t is (WRITE_SRR0, WRITE_SRR1);
  78
  79     -- This needs to die...
  80     type ctrl_t is record
  81         tb: std_ulogic_vector(63 downto 0);
  82         dec: std_ulogic_vector(63 downto 0);
  83         msr: std_ulogic_vector(63 downto 0);
  84         irq_state : irq_state_t;
  85         irq_nia: std_ulogic_vector(63 downto 0);
  86         srr1: std_ulogic_vector(63 downto 0);
  87     end record;
  88
  89     type Fetch1ToIcacheType is record
  90         req: std_ulogic;
  91         stop_mark: std_ulogic;
  92         nia: std_ulogic_vector(63 downto 0);
  93     end record;
  94
  95     type IcacheToFetch2Type is record
  96         valid: std_ulogic;
  97         stop_mark: std_ulogic;
  98         nia: std_ulogic_vector(63 downto 0);
  99         insn: std_ulogic_vector(31 downto 0);
 100     end record;
 101
 102     type Fetch2ToDecode1Type is record
 103         valid: std_ulogic;
 104         stop_mark : std_ulogic;
 105         nia: std_ulogic_vector(63 downto 0);
 106         insn: std_ulogic_vector(31 downto 0);
 107     end record;
 108     constant Fetch2ToDecode1Init : Fetch2ToDecode1Type := (valid => '0', stop_mark => '0', others => (others => '0'));
 109
 110     type Decode1ToDecode2Type is record
 111         valid: std_ulogic;
 112         stop_mark : std_ulogic;
 113         nia: std_ulogic_vector(63 downto 0);
 114         insn: std_ulogic_vector(31 downto 0);
 115         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
 116         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
 117         decode: decode_rom_t;
 118     end record;
 119     constant Decode1ToDecode2Init : Decode1ToDecode2Type := (valid => '0', stop_mark => '0', decode => decode_rom_init, others => (others => '0'));
 120
 121     type Decode2ToExecute1Type is record
 122         valid: std_ulogic;
 123         unit : unit_t;
 124         insn_type: insn_type_t;
 125         nia: std_ulogic_vector(63 downto 0);
 126         write_reg: gspr_index_t;
 127         read_reg1: gspr_index_t;
 128         read_reg2: gspr_index_t;
 129         read_data1: std_ulogic_vector(63 downto 0);
 130         read_data2: std_ulogic_vector(63 downto 0);
 131         read_data3: std_ulogic_vector(63 downto 0);
 132         bypass_data1: std_ulogic;
 133         bypass_data2: std_ulogic;
 134         bypass_data3: std_ulogic;
 135         cr: std_ulogic_vector(31 downto 0);
 136         xerc: xer_common_t;
 137         lr: std_ulogic;
 138         rc: std_ulogic;
 139         oe: std_ulogic;
 140         invert_a: std_ulogic;
 141         invert_out: std_ulogic;
 142         input_carry: carry_in_t;
 143         output_carry: std_ulogic;
 144         input_cr: std_ulogic;
 145         output_cr: std_ulogic;
 146         is_32bit: std_ulogic;
 147         is_signed: std_ulogic;
 148         insn: std_ulogic_vector(31 downto 0);
 149         data_len: std_ulogic_vector(3 downto 0);
 150         byte_reverse : std_ulogic;
 151         sign_extend : std_ulogic;                       -- do we need to sign extend?
 152         update : std_ulogic;                            -- is this an update instruction?
 153         reserve : std_ulogic;                           -- set for larx/stcx
 154     end record;
 155     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 156         (valid => '0', unit => NONE, insn_type => OP_ILLEGAL, bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
 157          lr => '0', rc => '0', oe => '0', invert_a => '0',
 158          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
 159          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0',
 160          byte_reverse => '0', sign_extend => '0', update => '0', others => (others => '0'));
 161
 162     type Execute1ToMultiplyType is record
 163         valid: std_ulogic;
 164         insn_type: insn_type_t;
 165         data1: std_ulogic_vector(64 downto 0);
 166         data2: std_ulogic_vector(64 downto 0);
 167         is_32bit: std_ulogic;
 168     end record;
 169     constant Execute1ToMultiplyInit : Execute1ToMultiplyType := (valid => '0', insn_type => OP_ILLEGAL,
 170                                                                  is_32bit => '0',
 171                                                                  others => (others => '0'));
 172
 173     type Execute1ToDividerType is record
 174         valid: std_ulogic;
 175         dividend: std_ulogic_vector(63 downto 0);
 176         divisor: std_ulogic_vector(63 downto 0);
 177         is_signed: std_ulogic;
 178         is_32bit: std_ulogic;
 179         is_extended: std_ulogic;
 180         is_modulus: std_ulogic;
 181         neg_result: std_ulogic;
 182     end record;
 183     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 184                                                               is_extended => '0', is_modulus => '0',
 185                                                               neg_result => '0', others => (others => '0'));
 186
 187     type Decode2ToRegisterFileType is record
 188         read1_enable : std_ulogic;
 189         read1_reg : gspr_index_t;
 190         read2_enable : std_ulogic;
 191         read2_reg : gspr_index_t;
 192         read3_enable : std_ulogic;
 193         read3_reg : gpr_index_t;
 194     end record;
 195
 196     type RegisterFileToDecode2Type is record
 197         read1_data : std_ulogic_vector(63 downto 0);
 198         read2_data : std_ulogic_vector(63 downto 0);
 199         read3_data : std_ulogic_vector(63 downto 0);
 200     end record;
 201
 202     type Decode2ToCrFileType is record
 203         read : std_ulogic;
 204     end record;
 205
 206     type CrFileToDecode2Type is record
 207         read_cr_data   : std_ulogic_vector(31 downto 0);
 208         read_xerc_data : xer_common_t;
 209     end record;
 210
 211     type Execute1ToFetch1Type is record
 212         redirect: std_ulogic;
 213         redirect_nia: std_ulogic_vector(63 downto 0);
 214     end record;
 215     constant Execute1ToFetch1TypeInit : Execute1ToFetch1Type := (redirect => '0', others => (others => '0'));
 216
 217     type Execute1ToLoadstore1Type is record
 218         valid : std_ulogic;
 219         op : insn_type_t;                               -- what ld/st or m[tf]spr or TLB op to do
 220         addr1 : std_ulogic_vector(63 downto 0);
 221         addr2 : std_ulogic_vector(63 downto 0);
 222         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 223         write_reg : gpr_index_t;
 224         length : std_ulogic_vector(3 downto 0);
 225         ci : std_ulogic;                                -- cache-inhibited load/store
 226         byte_reverse : std_ulogic;
 227         sign_extend : std_ulogic;                       -- do we need to sign extend?
 228         update : std_ulogic;                            -- is this an update instruction?
 229         update_reg : gpr_index_t;                       -- if so, the register to update
 230         xerc : xer_common_t;
 231         reserve : std_ulogic;                           -- set for larx/stcx.
 232         rc : std_ulogic;                                -- set for stcx.
 233         virt_mode : std_ulogic;                         -- do translation through TLB
 234         priv_mode : std_ulogic;                         -- privileged mode (MSR[PR] = 0)
 235         spr_num : spr_num_t;                            -- SPR number for mfspr/mtspr
 236     end record;
 237     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
 238                                                                      sign_extend => '0', update => '0', xerc => xerc_init,
 239                                                                      reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
 240                                                                      spr_num => 0, others => (others => '0'));
 241
 242     type Loadstore1ToExecute1Type is record
 243         exception : std_ulogic;
 244     end record;
 245
 246     type Loadstore1ToDcacheType is record
 247         valid : std_ulogic;
 248         load : std_ulogic;                              -- is this a load
 249         tlbie : std_ulogic;                             -- is this a tlbie
 250         dcbz : std_ulogic;
 251         nc : std_ulogic;
 252         reserve : std_ulogic;
 253         virt_mode : std_ulogic;
 254         priv_mode : std_ulogic;
 255         addr : std_ulogic_vector(63 downto 0);
 256         data : std_ulogic_vector(63 downto 0);
 257         byte_sel : std_ulogic_vector(7 downto 0);
 258     end record;
 259
 260     type DcacheToLoadstore1Type is record
 261         valid : std_ulogic;
 262         data : std_ulogic_vector(63 downto 0);
 263         store_done : std_ulogic;
 264         error : std_ulogic;
 265         tlb_miss : std_ulogic;
 266         perm_error : std_ulogic;
 267         rc_error : std_ulogic;
 268     end record;
 269
 270     type Loadstore1ToWritebackType is record
 271         valid : std_ulogic;
 272         write_enable: std_ulogic;
 273         write_reg : gpr_index_t;
 274         write_data : std_ulogic_vector(63 downto 0);
 275         xerc : xer_common_t;
 276         rc : std_ulogic;
 277         store_done : std_ulogic;
 278     end record;
 279     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType := (valid => '0', write_enable => '0', xerc => xerc_init,
 280                                                                        rc => '0', store_done => '0', others => (others => '0'));
 281
 282     type Execute1ToWritebackType is record
 283         valid: std_ulogic;
 284         rc : std_ulogic;
 285         write_enable : std_ulogic;
 286         write_reg: gspr_index_t;
 287         write_data: std_ulogic_vector(63 downto 0);
 288         write_cr_enable : std_ulogic;
 289         write_cr_mask : std_ulogic_vector(7 downto 0);
 290         write_cr_data : std_ulogic_vector(31 downto 0);
 291         write_xerc_enable : std_ulogic;
 292         xerc : xer_common_t;
 293         exc_write_enable : std_ulogic;
 294         exc_write_reg : gspr_index_t;
 295         exc_write_data : std_ulogic_vector(63 downto 0);
 296     end record;
 297     constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', write_enable => '0',
 298                                                                    write_cr_enable => '0', exc_write_enable => '0',
 299                                                                    write_xerc_enable => '0', xerc => xerc_init,
 300                                                                    others => (others => '0'));
 301
 302     type MultiplyToExecute1Type is record
 303         valid: std_ulogic;
 304         write_reg_data: std_ulogic_vector(63 downto 0);
 305         overflow : std_ulogic;
 306     end record;
 307     constant MultiplyToExecute1Init : MultiplyToExecute1Type := (valid => '0', overflow => '0',
 308                                                                  others => (others => '0'));
 309
 310     type DividerToExecute1Type is record
 311         valid: std_ulogic;
 312         write_reg_data: std_ulogic_vector(63 downto 0);
 313         overflow : std_ulogic;
 314     end record;
 315     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 316                                                                others => (others => '0'));
 317
 318     type WritebackToRegisterFileType is record
 319         write_reg : gspr_index_t;
 320         write_data : std_ulogic_vector(63 downto 0);
 321         write_enable : std_ulogic;
 322     end record;
 323     constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', others => (others => '0'));
 324
 325     type WritebackToCrFileType is record
 326         write_cr_enable : std_ulogic;
 327         write_cr_mask : std_ulogic_vector(7 downto 0);
 328         write_cr_data : std_ulogic_vector(31 downto 0);
 329         write_xerc_enable : std_ulogic;
 330         write_xerc_data : xer_common_t;
 331     end record;
 332     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 333                                                                write_xerc_data => xerc_init,
 334                                                                others => (others => '0'));
 335
 336     type XicsToExecute1Type is record
 337         irq : std_ulogic;
 338     end record;
 339
 340 end common;
 341
 342 package body common is
 343     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 344     begin
 345         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 346     end;
 347     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 348        variable n : integer range 0 to 31;
 349     begin
 350        case spr is
 351        when SPR_LR =>
 352            n := 0;
 353        when SPR_CTR =>
 354            n:= 1;
 355        when SPR_SRR0 =>
 356            n := 2;
 357        when SPR_SRR1 =>
 358            n := 3;
 359        when SPR_HSRR0 =>
 360            n := 4;
 361        when SPR_HSRR1 =>
 362            n := 5;
 363        when SPR_SPRG0 =>
 364            n := 6;
 365        when SPR_SPRG1 =>
 366            n := 7;
 367        when SPR_SPRG2 =>
 368            n := 8;
 369        when SPR_SPRG3 | SPR_SPRG3U =>
 370            n := 9;
 371        when SPR_HSPRG0 =>
 372            n := 10;
 373        when SPR_HSPRG1 =>
 374            n := 11;
 375        when SPR_XER =>
 376            n := 12;
 377        when others =>
 378            n := 0;
 379            return "000000";
 380        end case;
 381        return "1" & std_ulogic_vector(to_unsigned(n, 5));
 382     end;
 383
 384     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 385     begin
 386         return i(4 downto 0);
 387     end;
 388
 389     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 390     begin
 391         return "0" & i;
 392     end;
 393
 394     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 395     begin
 396         if s(5) = '1' then
 397             return s;
 398         else
 399             return gpr_to_gspr(g);
 400         end if;
 401     end;
 402
 403     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 404     begin
 405         return s(5);
 406     end;
 407 end common;