common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7
   8 package common is
   9     -- Processor Version Number
  10     constant PVR_MICROWATT  : std_ulogic_vector(31 downto 0) := x"00630000";
  11
  12     -- MSR bit numbers
  13     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  14     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  15     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  16     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  17     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  18     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  19     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  20
  21     -- SPR numbers
  22     subtype spr_num_t is integer range 0 to 1023;
  23
  24     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  25
  26     constant SPR_XER    : spr_num_t := 1;
  27     constant SPR_LR     : spr_num_t := 8;
  28     constant SPR_CTR    : spr_num_t := 9;
  29     constant SPR_TAR    : spr_num_t := 815;
  30     constant SPR_DSISR  : spr_num_t := 18;
  31     constant SPR_DAR    : spr_num_t := 19;
  32     constant SPR_TB     : spr_num_t := 268;
  33     constant SPR_TBU    : spr_num_t := 269;
  34     constant SPR_DEC    : spr_num_t := 22;
  35     constant SPR_SRR0   : spr_num_t := 26;
  36     constant SPR_SRR1   : spr_num_t := 27;
  37     constant SPR_CFAR   : spr_num_t := 28;
  38     constant SPR_HSRR0  : spr_num_t := 314;
  39     constant SPR_HSRR1  : spr_num_t := 315;
  40     constant SPR_SPRG0  : spr_num_t := 272;
  41     constant SPR_SPRG1  : spr_num_t := 273;
  42     constant SPR_SPRG2  : spr_num_t := 274;
  43     constant SPR_SPRG3  : spr_num_t := 275;
  44     constant SPR_SPRG3U : spr_num_t := 259;
  45     constant SPR_HSPRG0 : spr_num_t := 304;
  46     constant SPR_HSPRG1 : spr_num_t := 305;
  47     constant SPR_PID    : spr_num_t := 48;
  48     constant SPR_PRTBL  : spr_num_t := 720;
  49     constant SPR_PVR    : spr_num_t := 287;
  50
  51     -- GPR indices in the register file (GPR only)
  52     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  53
  54     -- Extended GPR indice (can hold an SPR)
  55     subtype gspr_index_t is std_ulogic_vector(5 downto 0);
  56
  57     -- Some SPRs are stored in the register file, they use the magic
  58     -- GPR numbers above 31.
  59     --
  60     -- The function fast_spr_num() returns the corresponding fast
  61     -- pseudo-GPR number for a given SPR number. The result MSB
  62     -- indicates if this is indeed a fast SPR. If clear, then
  63     -- the SPR is not stored in the GPR file.
  64     --
  65     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
  66
  67     -- Indices conversion functions
  68     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
  69     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
  70     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
  71     function is_fast_spr(s: gspr_index_t) return std_ulogic;
  72
  73     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
  74     -- in the CR file as a kind of CR extension (with a separate write
  75     -- control). The rest is stored as a fast SPR.
  76     type xer_common_t is record
  77         ca : std_ulogic;
  78         ca32 : std_ulogic;
  79         ov : std_ulogic;
  80         ov32 : std_ulogic;
  81         so : std_ulogic;
  82     end record;
  83     constant xerc_init : xer_common_t := (others => '0');
  84
  85     type irq_state_t is (WRITE_SRR0, WRITE_SRR1);
  86
  87     -- For now, fixed 16 sources, make this either a parametric
  88     -- package of some sort or an unconstrainted array.
  89     type ics_to_icp_t is record
  90         -- Level interrupts only, ICS just keeps prsenting the
  91         -- highest priority interrupt. Once handling edge, something
  92         -- smarter involving handshake & reject support will be needed
  93         src : std_ulogic_vector(3 downto 0);
  94         pri : std_ulogic_vector(7 downto 0);
  95     end record;
  96
  97     -- This needs to die...
  98     type ctrl_t is record
  99         tb: std_ulogic_vector(63 downto 0);
 100         dec: std_ulogic_vector(63 downto 0);
 101         msr: std_ulogic_vector(63 downto 0);
 102         cfar: std_ulogic_vector(63 downto 0);
 103         irq_state : irq_state_t;
 104         srr1: std_ulogic_vector(63 downto 0);
 105     end record;
 106
 107     type Fetch1ToIcacheType is record
 108         req: std_ulogic;
 109         virt_mode : std_ulogic;
 110         priv_mode : std_ulogic;
 111         big_endian : std_ulogic;
 112         stop_mark: std_ulogic;
 113         sequential: std_ulogic;
 114         nia: std_ulogic_vector(63 downto 0);
 115     end record;
 116
 117     type IcacheToDecode1Type is record
 118         valid: std_ulogic;
 119         stop_mark: std_ulogic;
 120         fetch_failed: std_ulogic;
 121         nia: std_ulogic_vector(63 downto 0);
 122         insn: std_ulogic_vector(31 downto 0);
 123     end record;
 124
 125     type Decode1ToDecode2Type is record
 126         valid: std_ulogic;
 127         stop_mark : std_ulogic;
 128         nia: std_ulogic_vector(63 downto 0);
 129         insn: std_ulogic_vector(31 downto 0);
 130         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
 131         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
 132         decode: decode_rom_t;
 133         br_pred: std_ulogic; -- Branch was predicted to be taken
 134     end record;
 135     constant Decode1ToDecode2Init : Decode1ToDecode2Type :=
 136         (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'),
 137          ispr1 => (others => '0'), ispr2 => (others => '0'), decode => decode_rom_init, br_pred => '0');
 138
 139     type Decode1ToFetch1Type is record
 140         redirect     : std_ulogic;
 141         redirect_nia : std_ulogic_vector(63 downto 0);
 142     end record;
 143
 144     type Decode2ToExecute1Type is record
 145         valid: std_ulogic;
 146         unit : unit_t;
 147         insn_type: insn_type_t;
 148         nia: std_ulogic_vector(63 downto 0);
 149         write_reg: gspr_index_t;
 150         read_reg1: gspr_index_t;
 151         read_reg2: gspr_index_t;
 152         read_data1: std_ulogic_vector(63 downto 0);
 153         read_data2: std_ulogic_vector(63 downto 0);
 154         read_data3: std_ulogic_vector(63 downto 0);
 155         bypass_data1: std_ulogic;
 156         bypass_data2: std_ulogic;
 157         bypass_data3: std_ulogic;
 158         cr: std_ulogic_vector(31 downto 0);
 159         bypass_cr : std_ulogic;
 160         xerc: xer_common_t;
 161         lr: std_ulogic;
 162         rc: std_ulogic;
 163         oe: std_ulogic;
 164         invert_a: std_ulogic;
 165         invert_out: std_ulogic;
 166         input_carry: carry_in_t;
 167         output_carry: std_ulogic;
 168         input_cr: std_ulogic;
 169         output_cr: std_ulogic;
 170         is_32bit: std_ulogic;
 171         is_signed: std_ulogic;
 172         insn: std_ulogic_vector(31 downto 0);
 173         data_len: std_ulogic_vector(3 downto 0);
 174         byte_reverse : std_ulogic;
 175         sign_extend : std_ulogic;                       -- do we need to sign extend?
 176         update : std_ulogic;                            -- is this an update instruction?
 177         reserve : std_ulogic;                           -- set for larx/stcx
 178         br_pred : std_ulogic;
 179     end record;
 180     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 181         (valid => '0', unit => NONE, insn_type => OP_ILLEGAL, bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
 182          bypass_cr => '0', lr => '0', rc => '0', oe => '0', invert_a => '0',
 183          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
 184          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0', br_pred => '0',
 185          byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'), read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'), cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'), others => (others => '0'));
 186
 187     type MultiplyInputType is record
 188         valid: std_ulogic;
 189         data1: std_ulogic_vector(63 downto 0);
 190         data2: std_ulogic_vector(63 downto 0);
 191         addend: std_ulogic_vector(127 downto 0);
 192         is_32bit: std_ulogic;
 193         not_result: std_ulogic;
 194     end record;
 195     constant MultiplyInputInit : MultiplyInputType := (valid => '0',
 196                                                        is_32bit => '0', not_result => '0',
 197                                                        others => (others => '0'));
 198
 199     type MultiplyOutputType is record
 200         valid: std_ulogic;
 201         result: std_ulogic_vector(127 downto 0);
 202         overflow : std_ulogic;
 203     end record;
 204     constant MultiplyOutputInit : MultiplyOutputType := (valid => '0', overflow => '0',
 205                                                          others => (others => '0'));
 206
 207     type Execute1ToDividerType is record
 208         valid: std_ulogic;
 209         dividend: std_ulogic_vector(63 downto 0);
 210         divisor: std_ulogic_vector(63 downto 0);
 211         is_signed: std_ulogic;
 212         is_32bit: std_ulogic;
 213         is_extended: std_ulogic;
 214         is_modulus: std_ulogic;
 215         neg_result: std_ulogic;
 216     end record;
 217     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 218                                                               is_extended => '0', is_modulus => '0',
 219                                                               neg_result => '0', others => (others => '0'));
 220
 221     type Decode2ToRegisterFileType is record
 222         read1_enable : std_ulogic;
 223         read1_reg : gspr_index_t;
 224         read2_enable : std_ulogic;
 225         read2_reg : gspr_index_t;
 226         read3_enable : std_ulogic;
 227         read3_reg : gpr_index_t;
 228     end record;
 229
 230     type RegisterFileToDecode2Type is record
 231         read1_data : std_ulogic_vector(63 downto 0);
 232         read2_data : std_ulogic_vector(63 downto 0);
 233         read3_data : std_ulogic_vector(63 downto 0);
 234     end record;
 235
 236     type Decode2ToCrFileType is record
 237         read : std_ulogic;
 238     end record;
 239
 240     type CrFileToDecode2Type is record
 241         read_cr_data   : std_ulogic_vector(31 downto 0);
 242         read_xerc_data : xer_common_t;
 243     end record;
 244
 245     type Execute1ToFetch1Type is record
 246         redirect: std_ulogic;
 247         virt_mode: std_ulogic;
 248         priv_mode: std_ulogic;
 249         big_endian: std_ulogic;
 250         mode_32bit: std_ulogic;
 251         redirect_nia: std_ulogic_vector(63 downto 0);
 252     end record;
 253     constant Execute1ToFetch1Init : Execute1ToFetch1Type := (redirect => '0', virt_mode => '0',
 254                                                              priv_mode => '0', big_endian => '0',
 255                                                              mode_32bit => '0', others => (others => '0'));
 256
 257     type Execute1ToLoadstore1Type is record
 258         valid : std_ulogic;
 259         op : insn_type_t;                               -- what ld/st or m[tf]spr or TLB op to do
 260         nia : std_ulogic_vector(63 downto 0);
 261         insn : std_ulogic_vector(31 downto 0);
 262         addr1 : std_ulogic_vector(63 downto 0);
 263         addr2 : std_ulogic_vector(63 downto 0);
 264         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 265         write_reg : gpr_index_t;
 266         length : std_ulogic_vector(3 downto 0);
 267         ci : std_ulogic;                                -- cache-inhibited load/store
 268         byte_reverse : std_ulogic;
 269         sign_extend : std_ulogic;                       -- do we need to sign extend?
 270         update : std_ulogic;                            -- is this an update instruction?
 271         update_reg : gpr_index_t;                       -- if so, the register to update
 272         xerc : xer_common_t;
 273         reserve : std_ulogic;                           -- set for larx/stcx.
 274         rc : std_ulogic;                                -- set for stcx.
 275         virt_mode : std_ulogic;                         -- do translation through TLB
 276         priv_mode : std_ulogic;                         -- privileged mode (MSR[PR] = 0)
 277         mode_32bit : std_ulogic;                        -- trim addresses to 32 bits
 278     end record;
 279     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
 280                                                                      sign_extend => '0', update => '0', xerc => xerc_init,
 281                                                                      reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
 282                                                                      nia => (others => '0'), insn => (others => '0'),
 283                                                                      addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'), length => (others => '0'),
 284                                                                      mode_32bit => '0', others => (others => '0'));
 285
 286     type Loadstore1ToExecute1Type is record
 287         busy : std_ulogic;
 288         exception : std_ulogic;
 289         alignment : std_ulogic;
 290         invalid : std_ulogic;
 291         perm_error : std_ulogic;
 292         rc_error : std_ulogic;
 293         badtree : std_ulogic;
 294         segment_fault : std_ulogic;
 295         instr_fault : std_ulogic;
 296     end record;
 297
 298     type Loadstore1ToDcacheType is record
 299         valid : std_ulogic;
 300         load : std_ulogic;                              -- is this a load
 301         dcbz : std_ulogic;
 302         nc : std_ulogic;
 303         reserve : std_ulogic;
 304         virt_mode : std_ulogic;
 305         priv_mode : std_ulogic;
 306         addr : std_ulogic_vector(63 downto 0);
 307         data : std_ulogic_vector(63 downto 0);
 308         byte_sel : std_ulogic_vector(7 downto 0);
 309     end record;
 310
 311     type DcacheToLoadstore1Type is record
 312         valid : std_ulogic;
 313         data : std_ulogic_vector(63 downto 0);
 314         store_done : std_ulogic;
 315         error : std_ulogic;
 316         cache_paradox : std_ulogic;
 317     end record;
 318
 319     type Loadstore1ToMmuType is record
 320         valid : std_ulogic;
 321         tlbie : std_ulogic;
 322         slbia : std_ulogic;
 323         mtspr : std_ulogic;
 324         iside : std_ulogic;
 325         load  : std_ulogic;
 326         priv  : std_ulogic;
 327         sprn  : std_ulogic_vector(9 downto 0);
 328         addr  : std_ulogic_vector(63 downto 0);
 329         rs    : std_ulogic_vector(63 downto 0);
 330     end record;
 331
 332     type MmuToLoadstore1Type is record
 333         done       : std_ulogic;
 334         err        : std_ulogic;
 335         invalid    : std_ulogic;
 336         badtree    : std_ulogic;
 337         segerr     : std_ulogic;
 338         perm_error : std_ulogic;
 339         rc_error   : std_ulogic;
 340         sprval     : std_ulogic_vector(63 downto 0);
 341     end record;
 342
 343     type MmuToDcacheType is record
 344         valid : std_ulogic;
 345         tlbie : std_ulogic;
 346         doall : std_ulogic;
 347         tlbld : std_ulogic;
 348         addr  : std_ulogic_vector(63 downto 0);
 349         pte   : std_ulogic_vector(63 downto 0);
 350     end record;
 351
 352     type DcacheToMmuType is record
 353         stall : std_ulogic;
 354         done  : std_ulogic;
 355         err   : std_ulogic;
 356         data  : std_ulogic_vector(63 downto 0);
 357     end record;
 358
 359     type MmuToIcacheType is record
 360         tlbld : std_ulogic;
 361         tlbie : std_ulogic;
 362         doall : std_ulogic;
 363         addr  : std_ulogic_vector(63 downto 0);
 364         pte   : std_ulogic_vector(63 downto 0);
 365     end record;
 366
 367     type Loadstore1ToWritebackType is record
 368         valid : std_ulogic;
 369         write_enable: std_ulogic;
 370         write_reg : gpr_index_t;
 371         write_data : std_ulogic_vector(63 downto 0);
 372         xerc : xer_common_t;
 373         rc : std_ulogic;
 374         store_done : std_ulogic;
 375     end record;
 376     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType := (valid => '0', write_enable => '0', xerc => xerc_init,
 377                                                                        rc => '0', store_done => '0', write_data => (others => '0'), others => (others => '0'));
 378
 379     type Execute1ToWritebackType is record
 380         valid: std_ulogic;
 381         rc : std_ulogic;
 382         mode_32bit : std_ulogic;
 383         write_enable : std_ulogic;
 384         write_reg: gspr_index_t;
 385         write_data: std_ulogic_vector(63 downto 0);
 386         write_cr_enable : std_ulogic;
 387         write_cr_mask : std_ulogic_vector(7 downto 0);
 388         write_cr_data : std_ulogic_vector(31 downto 0);
 389         write_xerc_enable : std_ulogic;
 390         xerc : xer_common_t;
 391         exc_write_enable : std_ulogic;
 392         exc_write_reg : gspr_index_t;
 393         exc_write_data : std_ulogic_vector(63 downto 0);
 394     end record;
 395     constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', mode_32bit => '0', write_enable => '0',
 396                                                                    write_cr_enable => '0', exc_write_enable => '0',
 397                                                                    write_xerc_enable => '0', xerc => xerc_init,
 398                                    write_data => (others => '0'), write_cr_mask => (others => '0'),
 399                                    write_cr_data => (others => '0'), write_reg => (others => '0'),
 400                                    exc_write_reg => (others => '0'), exc_write_data => (others => '0'));
 401
 402     type DividerToExecute1Type is record
 403         valid: std_ulogic;
 404         write_reg_data: std_ulogic_vector(63 downto 0);
 405         overflow : std_ulogic;
 406     end record;
 407     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 408                                                                others => (others => '0'));
 409
 410     type WritebackToRegisterFileType is record
 411         write_reg : gspr_index_t;
 412         write_data : std_ulogic_vector(63 downto 0);
 413         write_enable : std_ulogic;
 414     end record;
 415     constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
 416
 417     type WritebackToCrFileType is record
 418         write_cr_enable : std_ulogic;
 419         write_cr_mask : std_ulogic_vector(7 downto 0);
 420         write_cr_data : std_ulogic_vector(31 downto 0);
 421         write_xerc_enable : std_ulogic;
 422         write_xerc_data : xer_common_t;
 423     end record;
 424     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 425                                                                write_xerc_data => xerc_init,
 426                                                                write_cr_mask => (others => '0'),
 427                                                                write_cr_data => (others => '0'));
 428
 429 end common;
 430
 431 package body common is
 432     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 433     begin
 434         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 435     end;
 436     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 437        variable n : integer range 0 to 31;
 438        -- tmp variable introduced as workaround for VCS compilation
 439        -- simulation was failing with subtype constraint mismatch error
 440        -- see GitHub PR #173
 441        variable tmp : std_ulogic_vector(4 downto 0);
 442     begin
 443        case spr is
 444        when SPR_LR =>
 445            n := 0;
 446        when SPR_CTR =>
 447            n:= 1;
 448        when SPR_SRR0 =>
 449            n := 2;
 450        when SPR_SRR1 =>
 451            n := 3;
 452        when SPR_HSRR0 =>
 453            n := 4;
 454        when SPR_HSRR1 =>
 455            n := 5;
 456        when SPR_SPRG0 =>
 457            n := 6;
 458        when SPR_SPRG1 =>
 459            n := 7;
 460        when SPR_SPRG2 =>
 461            n := 8;
 462        when SPR_SPRG3 | SPR_SPRG3U =>
 463            n := 9;
 464        when SPR_HSPRG0 =>
 465            n := 10;
 466        when SPR_HSPRG1 =>
 467            n := 11;
 468        when SPR_XER =>
 469            n := 12;
 470        when SPR_TAR =>
 471            n := 13;
 472        when others =>
 473            n := 0;
 474            return "000000";
 475        end case;
 476        tmp := std_ulogic_vector(to_unsigned(n, 5));
 477        return "1" & tmp;
 478     end;
 479
 480     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 481     begin
 482         return i(4 downto 0);
 483     end;
 484
 485     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 486     begin
 487         return "0" & i;
 488     end;
 489
 490     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 491     begin
 492         if s(5) = '1' then
 493             return s;
 494         else
 495             return gpr_to_gspr(g);
 496         end if;
 497     end;
 498
 499     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 500     begin
 501         return s(5);
 502     end;
 503 end common;