core.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core is
  10     generic (
  11         SIM : boolean := false;
  12         DISABLE_FLATTEN : boolean := false;
  13         EX1_BYPASS : boolean := true;
  14         HAS_FPU : boolean := true;
  15         HAS_BTC : boolean := true;
  16         ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
  17         LOG_LENGTH : natural := 512
  18         );
  19     port (
  20         clk          : in std_ulogic;
  21         rst          : in std_ulogic;
  22
  23         -- Alternate reset (0xffff0000) for use by DRAM init fw
  24         alt_reset    : in std_ulogic;
  25
  26         -- Wishbone interface
  27         wishbone_insn_in  : in wishbone_slave_out;
  28         wishbone_insn_out : out wishbone_master_out;
  29
  30         wishbone_data_in  : in wishbone_slave_out;
  31         wishbone_data_out : out wishbone_master_out;
  32
  33         dmi_addr        : in std_ulogic_vector(3 downto 0);
  34         dmi_din         : in std_ulogic_vector(63 downto 0);
  35         dmi_dout        : out std_ulogic_vector(63 downto 0);
  36         dmi_req         : in std_ulogic;
  37         dmi_wr          : in std_ulogic;
  38         dmi_ack         : out std_ulogic;
  39
  40         ext_irq         : in std_ulogic;
  41
  42         terminated_out   : out std_logic
  43         );
  44 end core;
  45
  46 architecture behave of core is
  47     -- icache signals
  48     signal fetch1_to_icache : Fetch1ToIcacheType;
  49     signal icache_to_decode1 : IcacheToDecode1Type;
  50     signal mmu_to_icache : MmuToIcacheType;
  51
  52     -- decode signals
  53     signal decode1_to_decode2: Decode1ToDecode2Type;
  54     signal decode1_to_fetch1: Decode1ToFetch1Type;
  55     signal decode2_to_execute1: Decode2ToExecute1Type;
  56
  57     -- register file signals
  58     signal register_file_to_decode2: RegisterFileToDecode2Type;
  59     signal decode2_to_register_file: Decode2ToRegisterFileType;
  60     signal writeback_to_register_file: WritebackToRegisterFileType;
  61
  62     -- CR file signals
  63     signal decode2_to_cr_file: Decode2ToCrFileType;
  64     signal cr_file_to_decode2: CrFileToDecode2Type;
  65     signal writeback_to_cr_file: WritebackToCrFileType;
  66
  67     -- execute signals
  68     signal execute1_to_writeback: Execute1ToWritebackType;
  69     signal execute1_to_fetch1: Execute1ToFetch1Type;
  70     signal execute1_bypass: bypass_data_t;
  71
  72     -- load store signals
  73     signal execute1_to_loadstore1: Execute1ToLoadstore1Type;
  74     signal loadstore1_to_execute1: Loadstore1ToExecute1Type;
  75     signal loadstore1_to_writeback: Loadstore1ToWritebackType;
  76     signal loadstore1_to_mmu: Loadstore1ToMmuType;
  77     signal mmu_to_loadstore1: MmuToLoadstore1Type;
  78
  79     -- dcache signals
  80     signal loadstore1_to_dcache: Loadstore1ToDcacheType;
  81     signal dcache_to_loadstore1: DcacheToLoadstore1Type;
  82     signal mmu_to_dcache: MmuToDcacheType;
  83     signal dcache_to_mmu: DcacheToMmuType;
  84
  85     -- FPU signals
  86     signal execute1_to_fpu: Execute1ToFPUType;
  87     signal fpu_to_execute1: FPUToExecute1Type;
  88     signal fpu_to_writeback: FPUToWritebackType;
  89
  90     -- local signals
  91     signal fetch1_stall_in : std_ulogic;
  92     signal icache_stall_out : std_ulogic;
  93     signal icache_stall_in : std_ulogic;
  94     signal decode1_stall_in : std_ulogic;
  95     signal decode1_busy     : std_ulogic;
  96     signal decode2_busy_in : std_ulogic;
  97     signal decode2_stall_out : std_ulogic;
  98     signal ex1_icache_inval: std_ulogic;
  99     signal ex1_busy_out: std_ulogic;
 100     signal dcache_stall_out: std_ulogic;
 101
 102     signal flush: std_ulogic;
 103     signal decode1_flush: std_ulogic;
 104     signal fetch1_flush: std_ulogic;
 105
 106     signal complete: instr_tag_t;
 107     signal terminate: std_ulogic;
 108     signal core_rst: std_ulogic;
 109     signal icache_inv: std_ulogic;
 110
 111     -- Delayed/Latched resets and alt_reset
 112     signal rst_fetch1  : std_ulogic := '1';
 113     signal rst_fetch2  : std_ulogic := '1';
 114     signal rst_icache  : std_ulogic := '1';
 115     signal rst_dcache  : std_ulogic := '1';
 116     signal rst_dec1    : std_ulogic := '1';
 117     signal rst_dec2    : std_ulogic := '1';
 118     signal rst_ex1     : std_ulogic := '1';
 119     signal rst_fpu     : std_ulogic := '1';
 120     signal rst_ls1     : std_ulogic := '1';
 121     signal rst_dbg     : std_ulogic := '1';
 122     signal alt_reset_d : std_ulogic;
 123
 124     signal sim_cr_dump: std_ulogic;
 125
 126     -- Debug actions
 127     signal dbg_core_stop: std_ulogic;
 128     signal dbg_core_rst: std_ulogic;
 129     signal dbg_icache_rst: std_ulogic;
 130
 131     signal dbg_gpr_req : std_ulogic;
 132     signal dbg_gpr_ack : std_ulogic;
 133     signal dbg_gpr_addr : gspr_index_t;
 134     signal dbg_gpr_data : std_ulogic_vector(63 downto 0);
 135
 136     signal msr : std_ulogic_vector(63 downto 0);
 137
 138     -- Debug status
 139     signal dbg_core_is_stopped: std_ulogic;
 140
 141     -- Logging signals
 142     signal log_data    : std_ulogic_vector(255 downto 0);
 143     signal log_rd_addr : std_ulogic_vector(31 downto 0);
 144     signal log_wr_addr : std_ulogic_vector(31 downto 0);
 145     signal log_rd_data : std_ulogic_vector(63 downto 0);
 146
 147     function keep_h(disable : boolean) return string is
 148     begin
 149         if disable then
 150             return "yes";
 151         else
 152             return "no";
 153         end if;
 154     end function;
 155     attribute keep_hierarchy : string;
 156     attribute keep_hierarchy of fetch1_0 : label is keep_h(DISABLE_FLATTEN);
 157     attribute keep_hierarchy of icache_0 : label is keep_h(DISABLE_FLATTEN);
 158     attribute keep_hierarchy of decode1_0 : label is keep_h(DISABLE_FLATTEN);
 159     attribute keep_hierarchy of decode2_0 : label is keep_h(DISABLE_FLATTEN);
 160     attribute keep_hierarchy of register_file_0 : label is keep_h(DISABLE_FLATTEN);
 161     attribute keep_hierarchy of cr_file_0 : label is keep_h(DISABLE_FLATTEN);
 162     attribute keep_hierarchy of execute1_0 : label is keep_h(DISABLE_FLATTEN);
 163     attribute keep_hierarchy of loadstore1_0 : label is keep_h(DISABLE_FLATTEN);
 164     attribute keep_hierarchy of mmu_0 : label is keep_h(DISABLE_FLATTEN);
 165     attribute keep_hierarchy of dcache_0 : label is keep_h(DISABLE_FLATTEN);
 166     attribute keep_hierarchy of writeback_0 : label is keep_h(DISABLE_FLATTEN);
 167     attribute keep_hierarchy of debug_0 : label is keep_h(DISABLE_FLATTEN);
 168 begin
 169
 170     core_rst <= dbg_core_rst or rst;
 171
 172     resets: process(clk)
 173     begin
 174         if rising_edge(clk) then
 175             rst_fetch1  <= core_rst;
 176             rst_fetch2  <= core_rst;
 177             rst_icache  <= core_rst;
 178             rst_dcache  <= core_rst;
 179             rst_dec1    <= core_rst;
 180             rst_dec2    <= core_rst;
 181             rst_ex1     <= core_rst;
 182             rst_fpu     <= core_rst;
 183             rst_ls1     <= core_rst;
 184             rst_dbg     <= rst;
 185             alt_reset_d <= alt_reset;
 186         end if;
 187     end process;
 188
 189     fetch1_0: entity work.fetch1
 190         generic map (
 191             RESET_ADDRESS => (others => '0'),
 192             ALT_RESET_ADDRESS => ALT_RESET_ADDRESS,
 193             HAS_BTC => HAS_BTC
 194             )
 195         port map (
 196             clk => clk,
 197             rst => rst_fetch1,
 198             alt_reset_in => alt_reset_d,
 199             stall_in => fetch1_stall_in,
 200             flush_in => fetch1_flush,
 201             inval_btc => ex1_icache_inval or mmu_to_icache.tlbie,
 202             stop_in => dbg_core_stop,
 203             d_in => decode1_to_fetch1,
 204             e_in => execute1_to_fetch1,
 205             i_out => fetch1_to_icache,
 206             log_out => log_data(42 downto 0)
 207             );
 208
 209     fetch1_stall_in <= icache_stall_out or decode1_busy;
 210     fetch1_flush <= flush or decode1_flush;
 211
 212     icache_0: entity work.icache
 213         generic map(
 214             SIM => SIM,
 215             LINE_SIZE => 64,
 216             NUM_LINES => 64,
 217             NUM_WAYS => 2,
 218             LOG_LENGTH => LOG_LENGTH
 219             )
 220         port map(
 221             clk => clk,
 222             rst => rst_icache,
 223             i_in => fetch1_to_icache,
 224             i_out => icache_to_decode1,
 225             m_in => mmu_to_icache,
 226             flush_in => fetch1_flush,
 227             inval_in => dbg_icache_rst or ex1_icache_inval,
 228             stall_in => icache_stall_in,
 229             stall_out => icache_stall_out,
 230             wishbone_out => wishbone_insn_out,
 231             wishbone_in => wishbone_insn_in,
 232             log_out => log_data(96 downto 43)
 233             );
 234
 235     icache_stall_in <= decode1_busy;
 236
 237     decode1_0: entity work.decode1
 238         generic map(
 239             HAS_FPU => HAS_FPU,
 240             LOG_LENGTH => LOG_LENGTH
 241             )
 242         port map (
 243             clk => clk,
 244             rst => rst_dec1,
 245             stall_in => decode1_stall_in,
 246             flush_in => flush,
 247             flush_out => decode1_flush,
 248             busy_out => decode1_busy,
 249             f_in => icache_to_decode1,
 250             d_out => decode1_to_decode2,
 251             f_out => decode1_to_fetch1,
 252             log_out => log_data(109 downto 97)
 253             );
 254
 255     decode1_stall_in <= decode2_stall_out;
 256
 257     decode2_0: entity work.decode2
 258         generic map (
 259             EX1_BYPASS => EX1_BYPASS,
 260             HAS_FPU => HAS_FPU,
 261             LOG_LENGTH => LOG_LENGTH
 262             )
 263         port map (
 264             clk => clk,
 265             rst => rst_dec2,
 266             busy_in => decode2_busy_in,
 267             stall_out => decode2_stall_out,
 268             flush_in => flush,
 269             complete_in => complete,
 270             stopped_out => dbg_core_is_stopped,
 271             d_in => decode1_to_decode2,
 272             e_out => decode2_to_execute1,
 273             r_in => register_file_to_decode2,
 274             r_out => decode2_to_register_file,
 275             c_in => cr_file_to_decode2,
 276             c_out => decode2_to_cr_file,
 277             execute_bypass => execute1_bypass,
 278             log_out => log_data(119 downto 110)
 279             );
 280     decode2_busy_in <= ex1_busy_out;
 281
 282     register_file_0: entity work.register_file
 283         generic map (
 284             SIM => SIM,
 285             HAS_FPU => HAS_FPU,
 286             LOG_LENGTH => LOG_LENGTH
 287             )
 288         port map (
 289             clk => clk,
 290             d_in => decode2_to_register_file,
 291             d_out => register_file_to_decode2,
 292             w_in => writeback_to_register_file,
 293             dbg_gpr_req => dbg_gpr_req,
 294             dbg_gpr_ack => dbg_gpr_ack,
 295             dbg_gpr_addr => dbg_gpr_addr,
 296             dbg_gpr_data => dbg_gpr_data,
 297             sim_dump => terminate,
 298             sim_dump_done => sim_cr_dump,
 299             log_out => log_data(255 downto 184)
 300             );
 301
 302     cr_file_0: entity work.cr_file
 303         generic map (
 304             SIM => SIM,
 305             LOG_LENGTH => LOG_LENGTH
 306             )
 307         port map (
 308             clk => clk,
 309             d_in => decode2_to_cr_file,
 310             d_out => cr_file_to_decode2,
 311             w_in => writeback_to_cr_file,
 312             sim_dump => sim_cr_dump,
 313             log_out => log_data(183 downto 171)
 314             );
 315
 316     execute1_0: entity work.execute1
 317         generic map (
 318             EX1_BYPASS => EX1_BYPASS,
 319             HAS_FPU => HAS_FPU,
 320             LOG_LENGTH => LOG_LENGTH
 321             )
 322         port map (
 323             clk => clk,
 324             rst => rst_ex1,
 325             flush_out => flush,
 326             busy_out => ex1_busy_out,
 327             e_in => decode2_to_execute1,
 328             l_in => loadstore1_to_execute1,
 329             fp_in => fpu_to_execute1,
 330             ext_irq_in => ext_irq,
 331             l_out => execute1_to_loadstore1,
 332             f_out => execute1_to_fetch1,
 333             fp_out => execute1_to_fpu,
 334             e_out => execute1_to_writeback,
 335             bypass_data => execute1_bypass,
 336             icache_inval => ex1_icache_inval,
 337             dbg_msr_out => msr,
 338             terminate_out => terminate,
 339             log_out => log_data(134 downto 120),
 340             log_rd_addr => log_rd_addr,
 341             log_rd_data => log_rd_data,
 342             log_wr_addr => log_wr_addr
 343             );
 344
 345     with_fpu: if HAS_FPU generate
 346     begin
 347         fpu_0: entity work.fpu
 348             port map (
 349                 clk => clk,
 350                 rst => rst_fpu,
 351                 e_in => execute1_to_fpu,
 352                 e_out => fpu_to_execute1,
 353                 w_out => fpu_to_writeback
 354                 );
 355     end generate;
 356
 357     no_fpu: if not HAS_FPU generate
 358     begin
 359         fpu_to_execute1 <= FPUToExecute1Init;
 360         fpu_to_writeback <= FPUToWritebackInit;
 361     end generate;
 362
 363     loadstore1_0: entity work.loadstore1
 364         generic map (
 365             HAS_FPU => HAS_FPU,
 366             LOG_LENGTH => LOG_LENGTH
 367             )
 368         port map (
 369             clk => clk,
 370             rst => rst_ls1,
 371             l_in => execute1_to_loadstore1,
 372             e_out => loadstore1_to_execute1,
 373             l_out => loadstore1_to_writeback,
 374             d_out => loadstore1_to_dcache,
 375             d_in => dcache_to_loadstore1,
 376             m_out => loadstore1_to_mmu,
 377             m_in => mmu_to_loadstore1,
 378             dc_stall => dcache_stall_out,
 379             log_out => log_data(149 downto 140)
 380             );
 381
 382     mmu_0: entity work.mmu
 383         port map (
 384             clk => clk,
 385             rst => core_rst,
 386             l_in => loadstore1_to_mmu,
 387             l_out => mmu_to_loadstore1,
 388             d_out => mmu_to_dcache,
 389             d_in => dcache_to_mmu,
 390             i_out => mmu_to_icache
 391             );
 392
 393     dcache_0: entity work.dcache
 394         generic map(
 395             LINE_SIZE => 64,
 396             NUM_LINES => 64,
 397             NUM_WAYS => 2,
 398             LOG_LENGTH => LOG_LENGTH
 399             )
 400         port map (
 401             clk => clk,
 402             rst => rst_dcache,
 403             d_in => loadstore1_to_dcache,
 404             d_out => dcache_to_loadstore1,
 405             m_in => mmu_to_dcache,
 406             m_out => dcache_to_mmu,
 407             stall_out => dcache_stall_out,
 408             wishbone_in => wishbone_data_in,
 409             wishbone_out => wishbone_data_out,
 410             log_out => log_data(170 downto 151)
 411             );
 412
 413     writeback_0: entity work.writeback
 414         port map (
 415             clk => clk,
 416             e_in => execute1_to_writeback,
 417             l_in => loadstore1_to_writeback,
 418             fp_in => fpu_to_writeback,
 419             w_out => writeback_to_register_file,
 420             c_out => writeback_to_cr_file,
 421             complete_out => complete
 422             );
 423
 424     log_data(150) <= '0';
 425     log_data(139 downto 135) <= "00000";
 426
 427     debug_0: entity work.core_debug
 428         generic map (
 429             LOG_LENGTH => LOG_LENGTH
 430             )
 431         port map (
 432             clk => clk,
 433             rst => rst_dbg,
 434             dmi_addr => dmi_addr,
 435             dmi_din => dmi_din,
 436             dmi_dout => dmi_dout,
 437             dmi_req => dmi_req,
 438             dmi_wr => dmi_wr,
 439             dmi_ack => dmi_ack,
 440             core_stop => dbg_core_stop,
 441             core_rst => dbg_core_rst,
 442             icache_rst => dbg_icache_rst,
 443             terminate => terminate,
 444             core_stopped => dbg_core_is_stopped,
 445             nia => fetch1_to_icache.nia,
 446             msr => msr,
 447             dbg_gpr_req => dbg_gpr_req,
 448             dbg_gpr_ack => dbg_gpr_ack,
 449             dbg_gpr_addr => dbg_gpr_addr,
 450             dbg_gpr_data => dbg_gpr_data,
 451             log_data => log_data,
 452             log_read_addr => log_rd_addr,
 453             log_read_data => log_rd_data,
 454             log_write_addr => log_wr_addr,
 455             terminated_out => terminated_out
 456             );
 457
 458 end behave;