core.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core is
  10     generic (
  11         SIM : boolean := false;
  12         DISABLE_FLATTEN : boolean := false;
  13         EX1_BYPASS : boolean := true;
  14         ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0')
  15         );
  16     port (
  17         clk          : in std_ulogic;
  18         rst          : in std_ulogic;
  19
  20         -- Alternate reset (0xffff0000) for use by DRAM init fw
  21         alt_reset    : in std_ulogic;
  22
  23         -- Wishbone interface
  24         wishbone_insn_in  : in wishbone_slave_out;
  25         wishbone_insn_out : out wishbone_master_out;
  26
  27         wishbone_data_in  : in wishbone_slave_out;
  28         wishbone_data_out : out wishbone_master_out;
  29
  30         dmi_addr        : in std_ulogic_vector(3 downto 0);
  31         dmi_din         : in std_ulogic_vector(63 downto 0);
  32         dmi_dout        : out std_ulogic_vector(63 downto 0);
  33         dmi_req         : in std_ulogic;
  34         dmi_wr          : in std_ulogic;
  35         dmi_ack         : out std_ulogic;
  36
  37         xics_in         : in XicsToExecute1Type;
  38
  39         terminated_out   : out std_logic
  40         );
  41 end core;
  42
  43 architecture behave of core is
  44     -- fetch signals
  45     signal fetch2_to_decode1: Fetch2ToDecode1Type;
  46
  47     -- icache signals
  48     signal fetch1_to_icache : Fetch1ToIcacheType;
  49     signal icache_to_fetch2 : IcacheToFetch2Type;
  50
  51     -- decode signals
  52     signal decode1_to_decode2: Decode1ToDecode2Type;
  53     signal decode2_to_execute1: Decode2ToExecute1Type;
  54
  55     -- register file signals
  56     signal register_file_to_decode2: RegisterFileToDecode2Type;
  57     signal decode2_to_register_file: Decode2ToRegisterFileType;
  58     signal writeback_to_register_file: WritebackToRegisterFileType;
  59
  60     -- CR file signals
  61     signal decode2_to_cr_file: Decode2ToCrFileType;
  62     signal cr_file_to_decode2: CrFileToDecode2Type;
  63     signal writeback_to_cr_file: WritebackToCrFileType;
  64
  65     -- execute signals
  66     signal execute1_to_writeback: Execute1ToWritebackType;
  67     signal execute1_to_fetch1: Execute1ToFetch1Type;
  68
  69     -- load store signals
  70     signal execute1_to_loadstore1: Execute1ToLoadstore1Type;
  71     signal loadstore1_to_writeback: Loadstore1ToWritebackType;
  72
  73     -- dcache signals
  74     signal loadstore1_to_dcache: Loadstore1ToDcacheType;
  75     signal dcache_to_loadstore1: DcacheToLoadstore1Type;
  76
  77     -- local signals
  78     signal fetch1_stall_in : std_ulogic;
  79     signal icache_stall_out : std_ulogic;
  80     signal fetch2_stall_in : std_ulogic;
  81     signal decode1_stall_in : std_ulogic;
  82     signal decode2_stall_in : std_ulogic;
  83     signal decode2_stall_out : std_ulogic;
  84     signal ex1_icache_inval: std_ulogic;
  85     signal ex1_stall_out: std_ulogic;
  86     signal ls1_stall_out: std_ulogic;
  87     signal dcache_stall_out: std_ulogic;
  88
  89     signal flush: std_ulogic;
  90
  91     signal complete: std_ulogic;
  92     signal terminate: std_ulogic;
  93     signal core_rst: std_ulogic;
  94     signal icache_rst: std_ulogic;
  95
  96     signal sim_cr_dump: std_ulogic;
  97
  98     -- Debug actions
  99     signal dbg_core_stop: std_ulogic;
 100     signal dbg_core_rst: std_ulogic;
 101     signal dbg_icache_rst: std_ulogic;
 102
 103     -- Debug status
 104     signal dbg_core_is_stopped: std_ulogic;
 105
 106     function keep_h(disable : boolean) return string is
 107     begin
 108         if disable then
 109             return "yes";
 110         else
 111             return "no";
 112         end if;
 113     end function;
 114     attribute keep_hierarchy : string;
 115     attribute keep_hierarchy of fetch1_0 : label is keep_h(DISABLE_FLATTEN);
 116     attribute keep_hierarchy of icache_0 : label is keep_h(DISABLE_FLATTEN);
 117     attribute keep_hierarchy of fetch2_0 : label is keep_h(DISABLE_FLATTEN);
 118     attribute keep_hierarchy of decode1_0 : label is keep_h(DISABLE_FLATTEN);
 119     attribute keep_hierarchy of decode2_0 : label is keep_h(DISABLE_FLATTEN);
 120     attribute keep_hierarchy of register_file_0 : label is keep_h(DISABLE_FLATTEN);
 121     attribute keep_hierarchy of cr_file_0 : label is keep_h(DISABLE_FLATTEN);
 122     attribute keep_hierarchy of execute1_0 : label is keep_h(DISABLE_FLATTEN);
 123     attribute keep_hierarchy of loadstore1_0 : label is keep_h(DISABLE_FLATTEN);
 124     attribute keep_hierarchy of dcache_0 : label is keep_h(DISABLE_FLATTEN);
 125     attribute keep_hierarchy of writeback_0 : label is keep_h(DISABLE_FLATTEN);
 126     attribute keep_hierarchy of debug_0 : label is keep_h(DISABLE_FLATTEN);
 127 begin
 128
 129     core_rst <= dbg_core_rst or rst;
 130
 131     fetch1_0: entity work.fetch1
 132         generic map (
 133             RESET_ADDRESS => (others => '0'),
 134             ALT_RESET_ADDRESS => ALT_RESET_ADDRESS
 135             )
 136         port map (
 137             clk => clk,
 138             rst => core_rst,
 139             alt_reset_in => alt_reset,
 140             stall_in => fetch1_stall_in,
 141             flush_in => flush,
 142             stop_in => dbg_core_stop,
 143             e_in => execute1_to_fetch1,
 144             i_out => fetch1_to_icache
 145             );
 146
 147     fetch1_stall_in <= icache_stall_out or decode2_stall_out;
 148
 149     icache_0: entity work.icache
 150         generic map(
 151             SIM => SIM,
 152             LINE_SIZE => 64,
 153             NUM_LINES => 32,
 154             NUM_WAYS => 2
 155             )
 156         port map(
 157             clk => clk,
 158             rst => icache_rst,
 159             i_in => fetch1_to_icache,
 160             i_out => icache_to_fetch2,
 161             flush_in => flush,
 162             stall_out => icache_stall_out,
 163             wishbone_out => wishbone_insn_out,
 164             wishbone_in => wishbone_insn_in
 165             );
 166
 167     icache_rst <= rst or dbg_icache_rst or ex1_icache_inval;
 168
 169     fetch2_0: entity work.fetch2
 170         port map (
 171             clk => clk,
 172             rst => core_rst,
 173             stall_in => fetch2_stall_in,
 174             flush_in => flush,
 175             i_in => icache_to_fetch2,
 176             f_out => fetch2_to_decode1
 177             );
 178
 179     fetch2_stall_in <= decode2_stall_out;
 180
 181     decode1_0: entity work.decode1
 182         port map (
 183             clk => clk,
 184             rst => core_rst,
 185             stall_in => decode1_stall_in,
 186             flush_in => flush,
 187             f_in => fetch2_to_decode1,
 188             d_out => decode1_to_decode2
 189             );
 190
 191     decode1_stall_in <= decode2_stall_out;
 192
 193     decode2_0: entity work.decode2
 194         generic map (
 195             EX1_BYPASS => EX1_BYPASS
 196             )
 197         port map (
 198             clk => clk,
 199             rst => core_rst,
 200             stall_in => decode2_stall_in,
 201             stall_out => decode2_stall_out,
 202             flush_in => flush,
 203             complete_in => complete,
 204             stopped_out => dbg_core_is_stopped,
 205             d_in => decode1_to_decode2,
 206             e_out => decode2_to_execute1,
 207             r_in => register_file_to_decode2,
 208             r_out => decode2_to_register_file,
 209             c_in => cr_file_to_decode2,
 210             c_out => decode2_to_cr_file
 211             );
 212     decode2_stall_in <= ex1_stall_out or ls1_stall_out;
 213
 214     register_file_0: entity work.register_file
 215         generic map (
 216             SIM => SIM
 217             )
 218         port map (
 219             clk => clk,
 220             d_in => decode2_to_register_file,
 221             d_out => register_file_to_decode2,
 222             w_in => writeback_to_register_file,
 223             sim_dump => terminate,
 224             sim_dump_done => sim_cr_dump
 225             );
 226
 227     cr_file_0: entity work.cr_file
 228         generic map (
 229             SIM => SIM
 230             )
 231         port map (
 232             clk => clk,
 233             d_in => decode2_to_cr_file,
 234             d_out => cr_file_to_decode2,
 235             w_in => writeback_to_cr_file,
 236             sim_dump => sim_cr_dump
 237             );
 238
 239     execute1_0: entity work.execute1
 240         generic map (
 241             EX1_BYPASS => EX1_BYPASS
 242             )
 243         port map (
 244             clk => clk,
 245             rst => core_rst,
 246             flush_out => flush,
 247             stall_out => ex1_stall_out,
 248             e_in => decode2_to_execute1,
 249             i_in => xics_in,
 250             l_out => execute1_to_loadstore1,
 251             f_out => execute1_to_fetch1,
 252             e_out => execute1_to_writeback,
 253             icache_inval => ex1_icache_inval,
 254             terminate_out => terminate
 255             );
 256
 257     loadstore1_0: entity work.loadstore1
 258         port map (
 259             clk => clk,
 260             rst => core_rst,
 261             l_in => execute1_to_loadstore1,
 262             l_out => loadstore1_to_writeback,
 263             d_out => loadstore1_to_dcache,
 264             d_in => dcache_to_loadstore1,
 265             dc_stall => dcache_stall_out,
 266             stall_out => ls1_stall_out
 267             );
 268
 269     dcache_0: entity work.dcache
 270         generic map(
 271             LINE_SIZE => 64,
 272             NUM_LINES => 32,
 273             NUM_WAYS => 2
 274             )
 275         port map (
 276             clk => clk,
 277             rst => core_rst,
 278             d_in => loadstore1_to_dcache,
 279             d_out => dcache_to_loadstore1,
 280             stall_out => dcache_stall_out,
 281             wishbone_in => wishbone_data_in,
 282             wishbone_out => wishbone_data_out
 283             );
 284
 285     writeback_0: entity work.writeback
 286         port map (
 287             clk => clk,
 288             e_in => execute1_to_writeback,
 289             l_in => loadstore1_to_writeback,
 290             w_out => writeback_to_register_file,
 291             c_out => writeback_to_cr_file,
 292             complete_out => complete
 293             );
 294
 295     debug_0: entity work.core_debug
 296         port map (
 297             clk => clk,
 298             rst => rst,
 299             dmi_addr => dmi_addr,
 300             dmi_din => dmi_din,
 301             dmi_dout => dmi_dout,
 302             dmi_req => dmi_req,
 303             dmi_wr => dmi_wr,
 304             dmi_ack => dmi_ack,
 305             core_stop => dbg_core_stop,
 306             core_rst => dbg_core_rst,
 307             icache_rst => dbg_icache_rst,
 308             terminate => terminate,
 309             core_stopped => dbg_core_is_stopped,
 310             nia => fetch1_to_icache.nia,
 311             terminated_out => terminated_out
 312             );
 313
 314 end behave;