core.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core is
  10     generic (
  11         SIM : boolean := false;
  12         DISABLE_FLATTEN : boolean := false;
  13         EX1_BYPASS : boolean := true;
  14         ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0')
  15         );
  16     port (
  17         clk          : in std_ulogic;
  18         rst          : in std_ulogic;
  19
  20         -- Alternate reset (0xffff0000) for use by DRAM init fw
  21         alt_reset    : in std_ulogic;
  22
  23         -- Wishbone interface
  24         wishbone_insn_in  : in wishbone_slave_out;
  25         wishbone_insn_out : out wishbone_master_out;
  26
  27         wishbone_data_in  : in wishbone_slave_out;
  28         wishbone_data_out : out wishbone_master_out;
  29
  30         dmi_addr        : in std_ulogic_vector(3 downto 0);
  31         dmi_din         : in std_ulogic_vector(63 downto 0);
  32         dmi_dout        : out std_ulogic_vector(63 downto 0);
  33         dmi_req         : in std_ulogic;
  34         dmi_wr          : in std_ulogic;
  35         dmi_ack         : out std_ulogic;
  36
  37         xics_in         : in XicsToExecute1Type;
  38
  39         terminated_out   : out std_logic
  40         );
  41 end core;
  42
  43 architecture behave of core is
  44     -- fetch signals
  45     signal fetch2_to_decode1: Fetch2ToDecode1Type;
  46
  47     -- icache signals
  48     signal fetch1_to_icache : Fetch1ToIcacheType;
  49     signal icache_to_fetch2 : IcacheToFetch2Type;
  50     signal mmu_to_icache : MmuToIcacheType;
  51
  52     -- decode signals
  53     signal decode1_to_decode2: Decode1ToDecode2Type;
  54     signal decode2_to_execute1: Decode2ToExecute1Type;
  55
  56     -- register file signals
  57     signal register_file_to_decode2: RegisterFileToDecode2Type;
  58     signal decode2_to_register_file: Decode2ToRegisterFileType;
  59     signal writeback_to_register_file: WritebackToRegisterFileType;
  60
  61     -- CR file signals
  62     signal decode2_to_cr_file: Decode2ToCrFileType;
  63     signal cr_file_to_decode2: CrFileToDecode2Type;
  64     signal writeback_to_cr_file: WritebackToCrFileType;
  65
  66     -- execute signals
  67     signal execute1_to_writeback: Execute1ToWritebackType;
  68     signal execute1_to_fetch1: Execute1ToFetch1Type;
  69
  70     -- load store signals
  71     signal execute1_to_loadstore1: Execute1ToLoadstore1Type;
  72     signal loadstore1_to_execute1: Loadstore1ToExecute1Type;
  73     signal loadstore1_to_writeback: Loadstore1ToWritebackType;
  74     signal loadstore1_to_mmu: Loadstore1ToMmuType;
  75     signal mmu_to_loadstore1: MmuToLoadstore1Type;
  76
  77     -- dcache signals
  78     signal loadstore1_to_dcache: Loadstore1ToDcacheType;
  79     signal dcache_to_loadstore1: DcacheToLoadstore1Type;
  80     signal mmu_to_dcache: MmuToDcacheType;
  81     signal dcache_to_mmu: DcacheToMmuType;
  82
  83     -- local signals
  84     signal fetch1_stall_in : std_ulogic;
  85     signal icache_stall_out : std_ulogic;
  86     signal fetch2_stall_in : std_ulogic;
  87     signal decode1_stall_in : std_ulogic;
  88     signal decode2_stall_in : std_ulogic;
  89     signal decode2_stall_out : std_ulogic;
  90     signal ex1_icache_inval: std_ulogic;
  91     signal ex1_stall_out: std_ulogic;
  92     signal ls1_stall_out: std_ulogic;
  93     signal dcache_stall_out: std_ulogic;
  94
  95     signal flush: std_ulogic;
  96
  97     signal complete: std_ulogic;
  98     signal terminate: std_ulogic;
  99     signal core_rst: std_ulogic;
 100     signal icache_rst: std_ulogic;
 101
 102     signal sim_cr_dump: std_ulogic;
 103
 104     -- Debug actions
 105     signal dbg_core_stop: std_ulogic;
 106     signal dbg_core_rst: std_ulogic;
 107     signal dbg_icache_rst: std_ulogic;
 108
 109     signal dbg_gpr_req : std_ulogic;
 110     signal dbg_gpr_ack : std_ulogic;
 111     signal dbg_gpr_addr : gspr_index_t;
 112     signal dbg_gpr_data : std_ulogic_vector(63 downto 0);
 113
 114     signal msr : std_ulogic_vector(63 downto 0);
 115
 116     -- Debug status
 117     signal dbg_core_is_stopped: std_ulogic;
 118
 119     function keep_h(disable : boolean) return string is
 120     begin
 121         if disable then
 122             return "yes";
 123         else
 124             return "no";
 125         end if;
 126     end function;
 127     attribute keep_hierarchy : string;
 128     attribute keep_hierarchy of fetch1_0 : label is keep_h(DISABLE_FLATTEN);
 129     attribute keep_hierarchy of icache_0 : label is keep_h(DISABLE_FLATTEN);
 130     attribute keep_hierarchy of fetch2_0 : label is keep_h(DISABLE_FLATTEN);
 131     attribute keep_hierarchy of decode1_0 : label is keep_h(DISABLE_FLATTEN);
 132     attribute keep_hierarchy of decode2_0 : label is keep_h(DISABLE_FLATTEN);
 133     attribute keep_hierarchy of register_file_0 : label is keep_h(DISABLE_FLATTEN);
 134     attribute keep_hierarchy of cr_file_0 : label is keep_h(DISABLE_FLATTEN);
 135     attribute keep_hierarchy of execute1_0 : label is keep_h(DISABLE_FLATTEN);
 136     attribute keep_hierarchy of loadstore1_0 : label is keep_h(DISABLE_FLATTEN);
 137     attribute keep_hierarchy of mmu_0 : label is keep_h(DISABLE_FLATTEN);
 138     attribute keep_hierarchy of dcache_0 : label is keep_h(DISABLE_FLATTEN);
 139     attribute keep_hierarchy of writeback_0 : label is keep_h(DISABLE_FLATTEN);
 140     attribute keep_hierarchy of debug_0 : label is keep_h(DISABLE_FLATTEN);
 141 begin
 142
 143     core_rst <= dbg_core_rst or rst;
 144
 145     fetch1_0: entity work.fetch1
 146         generic map (
 147             RESET_ADDRESS => (others => '0'),
 148             ALT_RESET_ADDRESS => ALT_RESET_ADDRESS
 149             )
 150         port map (
 151             clk => clk,
 152             rst => core_rst,
 153             alt_reset_in => alt_reset,
 154             stall_in => fetch1_stall_in,
 155             flush_in => flush,
 156             stop_in => dbg_core_stop,
 157             e_in => execute1_to_fetch1,
 158             i_out => fetch1_to_icache
 159             );
 160
 161     fetch1_stall_in <= icache_stall_out or decode2_stall_out;
 162
 163     icache_0: entity work.icache
 164         generic map(
 165             SIM => SIM,
 166             LINE_SIZE => 64,
 167             NUM_LINES => 32,
 168             NUM_WAYS => 2
 169             )
 170         port map(
 171             clk => clk,
 172             rst => icache_rst,
 173             i_in => fetch1_to_icache,
 174             i_out => icache_to_fetch2,
 175             m_in => mmu_to_icache,
 176             flush_in => flush,
 177             stall_out => icache_stall_out,
 178             wishbone_out => wishbone_insn_out,
 179             wishbone_in => wishbone_insn_in
 180             );
 181
 182     icache_rst <= rst or dbg_icache_rst or ex1_icache_inval;
 183
 184     fetch2_0: entity work.fetch2
 185         port map (
 186             clk => clk,
 187             rst => core_rst,
 188             stall_in => fetch2_stall_in,
 189             flush_in => flush,
 190             i_in => icache_to_fetch2,
 191             f_out => fetch2_to_decode1
 192             );
 193
 194     fetch2_stall_in <= decode2_stall_out;
 195
 196     decode1_0: entity work.decode1
 197         port map (
 198             clk => clk,
 199             rst => core_rst,
 200             stall_in => decode1_stall_in,
 201             flush_in => flush,
 202             f_in => fetch2_to_decode1,
 203             d_out => decode1_to_decode2
 204             );
 205
 206     decode1_stall_in <= decode2_stall_out;
 207
 208     decode2_0: entity work.decode2
 209         generic map (
 210             EX1_BYPASS => EX1_BYPASS
 211             )
 212         port map (
 213             clk => clk,
 214             rst => core_rst,
 215             stall_in => decode2_stall_in,
 216             stall_out => decode2_stall_out,
 217             flush_in => flush,
 218             complete_in => complete,
 219             stopped_out => dbg_core_is_stopped,
 220             d_in => decode1_to_decode2,
 221             e_out => decode2_to_execute1,
 222             r_in => register_file_to_decode2,
 223             r_out => decode2_to_register_file,
 224             c_in => cr_file_to_decode2,
 225             c_out => decode2_to_cr_file
 226             );
 227     decode2_stall_in <= ex1_stall_out or ls1_stall_out;
 228
 229     register_file_0: entity work.register_file
 230         generic map (
 231             SIM => SIM
 232             )
 233         port map (
 234             clk => clk,
 235             d_in => decode2_to_register_file,
 236             d_out => register_file_to_decode2,
 237             w_in => writeback_to_register_file,
 238             dbg_gpr_req => dbg_gpr_req,
 239             dbg_gpr_ack => dbg_gpr_ack,
 240             dbg_gpr_addr => dbg_gpr_addr,
 241             dbg_gpr_data => dbg_gpr_data,
 242             sim_dump => terminate,
 243             sim_dump_done => sim_cr_dump
 244             );
 245
 246     cr_file_0: entity work.cr_file
 247         generic map (
 248             SIM => SIM
 249             )
 250         port map (
 251             clk => clk,
 252             d_in => decode2_to_cr_file,
 253             d_out => cr_file_to_decode2,
 254             w_in => writeback_to_cr_file,
 255             sim_dump => sim_cr_dump
 256             );
 257
 258     execute1_0: entity work.execute1
 259         generic map (
 260             EX1_BYPASS => EX1_BYPASS
 261             )
 262         port map (
 263             clk => clk,
 264             rst => core_rst,
 265             flush_out => flush,
 266             stall_out => ex1_stall_out,
 267             e_in => decode2_to_execute1,
 268             i_in => xics_in,
 269             l_in => loadstore1_to_execute1,
 270             l_out => execute1_to_loadstore1,
 271             f_out => execute1_to_fetch1,
 272             e_out => execute1_to_writeback,
 273             icache_inval => ex1_icache_inval,
 274             dbg_msr_out => msr,
 275             terminate_out => terminate
 276             );
 277
 278     loadstore1_0: entity work.loadstore1
 279         port map (
 280             clk => clk,
 281             rst => core_rst,
 282             l_in => execute1_to_loadstore1,
 283             e_out => loadstore1_to_execute1,
 284             l_out => loadstore1_to_writeback,
 285             d_out => loadstore1_to_dcache,
 286             d_in => dcache_to_loadstore1,
 287             m_out => loadstore1_to_mmu,
 288             m_in => mmu_to_loadstore1,
 289             dc_stall => dcache_stall_out,
 290             stall_out => ls1_stall_out
 291             );
 292
 293     mmu_0: entity work.mmu
 294         port map (
 295             clk => clk,
 296             rst => core_rst,
 297             l_in => loadstore1_to_mmu,
 298             l_out => mmu_to_loadstore1,
 299             d_out => mmu_to_dcache,
 300             d_in => dcache_to_mmu,
 301             i_out => mmu_to_icache
 302             );
 303
 304     dcache_0: entity work.dcache
 305         generic map(
 306             LINE_SIZE => 64,
 307             NUM_LINES => 32,
 308             NUM_WAYS => 2
 309             )
 310         port map (
 311             clk => clk,
 312             rst => core_rst,
 313             d_in => loadstore1_to_dcache,
 314             d_out => dcache_to_loadstore1,
 315             m_in => mmu_to_dcache,
 316             m_out => dcache_to_mmu,
 317             stall_out => dcache_stall_out,
 318             wishbone_in => wishbone_data_in,
 319             wishbone_out => wishbone_data_out
 320             );
 321
 322     writeback_0: entity work.writeback
 323         port map (
 324             clk => clk,
 325             e_in => execute1_to_writeback,
 326             l_in => loadstore1_to_writeback,
 327             w_out => writeback_to_register_file,
 328             c_out => writeback_to_cr_file,
 329             complete_out => complete
 330             );
 331
 332     debug_0: entity work.core_debug
 333         port map (
 334             clk => clk,
 335             rst => rst,
 336             dmi_addr => dmi_addr,
 337             dmi_din => dmi_din,
 338             dmi_dout => dmi_dout,
 339             dmi_req => dmi_req,
 340             dmi_wr => dmi_wr,
 341             dmi_ack => dmi_ack,
 342             core_stop => dbg_core_stop,
 343             core_rst => dbg_core_rst,
 344             icache_rst => dbg_icache_rst,
 345             terminate => terminate,
 346             core_stopped => dbg_core_is_stopped,
 347             nia => fetch1_to_icache.nia,
 348             msr => msr,
 349             dbg_gpr_req => dbg_gpr_req,
 350             dbg_gpr_ack => dbg_gpr_ack,
 351             dbg_gpr_addr => dbg_gpr_addr,
 352             dbg_gpr_data => dbg_gpr_data,
 353             terminated_out => terminated_out
 354             );
 355
 356 end behave;