core.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core is
  10     generic (
  11         SIM : boolean := false;
  12         DISABLE_FLATTEN : boolean := false;
  13         EX1_BYPASS : boolean := true;
  14         ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
  15         LOG_LENGTH : natural := 512
  16         );
  17     port (
  18         clk          : in std_ulogic;
  19         rst          : in std_ulogic;
  20
  21         -- Alternate reset (0xffff0000) for use by DRAM init fw
  22         alt_reset    : in std_ulogic;
  23
  24         -- Wishbone interface
  25         wishbone_insn_in  : in wishbone_slave_out;
  26         wishbone_insn_out : out wishbone_master_out;
  27
  28         wishbone_data_in  : in wishbone_slave_out;
  29         wishbone_data_out : out wishbone_master_out;
  30
  31         dmi_addr        : in std_ulogic_vector(3 downto 0);
  32         dmi_din         : in std_ulogic_vector(63 downto 0);
  33         dmi_dout        : out std_ulogic_vector(63 downto 0);
  34         dmi_req         : in std_ulogic;
  35         dmi_wr          : in std_ulogic;
  36         dmi_ack         : out std_ulogic;
  37
  38         ext_irq         : in std_ulogic;
  39
  40         terminated_out   : out std_logic
  41         );
  42 end core;
  43
  44 architecture behave of core is
  45     -- icache signals
  46     signal fetch1_to_icache : Fetch1ToIcacheType;
  47     signal icache_to_decode1 : IcacheToDecode1Type;
  48     signal mmu_to_icache : MmuToIcacheType;
  49
  50     -- decode signals
  51     signal decode1_to_decode2: Decode1ToDecode2Type;
  52     signal decode1_to_fetch1: Decode1ToFetch1Type;
  53     signal decode2_to_execute1: Decode2ToExecute1Type;
  54
  55     -- register file signals
  56     signal register_file_to_decode2: RegisterFileToDecode2Type;
  57     signal decode2_to_register_file: Decode2ToRegisterFileType;
  58     signal writeback_to_register_file: WritebackToRegisterFileType;
  59
  60     -- CR file signals
  61     signal decode2_to_cr_file: Decode2ToCrFileType;
  62     signal cr_file_to_decode2: CrFileToDecode2Type;
  63     signal writeback_to_cr_file: WritebackToCrFileType;
  64
  65     -- execute signals
  66     signal execute1_to_writeback: Execute1ToWritebackType;
  67     signal execute1_to_fetch1: Execute1ToFetch1Type;
  68
  69     -- load store signals
  70     signal execute1_to_loadstore1: Execute1ToLoadstore1Type;
  71     signal loadstore1_to_execute1: Loadstore1ToExecute1Type;
  72     signal loadstore1_to_writeback: Loadstore1ToWritebackType;
  73     signal loadstore1_to_mmu: Loadstore1ToMmuType;
  74     signal mmu_to_loadstore1: MmuToLoadstore1Type;
  75
  76     -- dcache signals
  77     signal loadstore1_to_dcache: Loadstore1ToDcacheType;
  78     signal dcache_to_loadstore1: DcacheToLoadstore1Type;
  79     signal mmu_to_dcache: MmuToDcacheType;
  80     signal dcache_to_mmu: DcacheToMmuType;
  81
  82     -- local signals
  83     signal fetch1_stall_in : std_ulogic;
  84     signal icache_stall_out : std_ulogic;
  85     signal icache_stall_in : std_ulogic;
  86     signal decode1_stall_in : std_ulogic;
  87     signal decode1_busy     : std_ulogic;
  88     signal decode2_busy_in : std_ulogic;
  89     signal decode2_stall_out : std_ulogic;
  90     signal ex1_icache_inval: std_ulogic;
  91     signal ex1_busy_out: std_ulogic;
  92     signal dcache_stall_out: std_ulogic;
  93
  94     signal flush: std_ulogic;
  95     signal decode1_flush: std_ulogic;
  96     signal fetch1_flush: std_ulogic;
  97
  98     signal complete: std_ulogic;
  99     signal terminate: std_ulogic;
 100     signal core_rst: std_ulogic;
 101     signal icache_inv: std_ulogic;
 102
 103     -- Delayed/Latched resets and alt_reset
 104     signal rst_fetch1  : std_ulogic := '1';
 105     signal rst_fetch2  : std_ulogic := '1';
 106     signal rst_icache  : std_ulogic := '1';
 107     signal rst_dcache  : std_ulogic := '1';
 108     signal rst_dec1    : std_ulogic := '1';
 109     signal rst_dec2    : std_ulogic := '1';
 110     signal rst_ex1     : std_ulogic := '1';
 111     signal rst_ls1     : std_ulogic := '1';
 112     signal rst_dbg     : std_ulogic := '1';
 113     signal alt_reset_d : std_ulogic;
 114
 115     signal sim_cr_dump: std_ulogic;
 116
 117     -- Debug actions
 118     signal dbg_core_stop: std_ulogic;
 119     signal dbg_core_rst: std_ulogic;
 120     signal dbg_icache_rst: std_ulogic;
 121
 122     signal dbg_gpr_req : std_ulogic;
 123     signal dbg_gpr_ack : std_ulogic;
 124     signal dbg_gpr_addr : gspr_index_t;
 125     signal dbg_gpr_data : std_ulogic_vector(63 downto 0);
 126
 127     signal msr : std_ulogic_vector(63 downto 0);
 128
 129     -- Debug status
 130     signal dbg_core_is_stopped: std_ulogic;
 131
 132     -- Logging signals
 133     signal log_data    : std_ulogic_vector(255 downto 0);
 134     signal log_rd_addr : std_ulogic_vector(31 downto 0);
 135     signal log_wr_addr : std_ulogic_vector(31 downto 0);
 136     signal log_rd_data : std_ulogic_vector(63 downto 0);
 137
 138     function keep_h(disable : boolean) return string is
 139     begin
 140         if disable then
 141             return "yes";
 142         else
 143             return "no";
 144         end if;
 145     end function;
 146     attribute keep_hierarchy : string;
 147     attribute keep_hierarchy of fetch1_0 : label is keep_h(DISABLE_FLATTEN);
 148     attribute keep_hierarchy of icache_0 : label is keep_h(DISABLE_FLATTEN);
 149     attribute keep_hierarchy of decode1_0 : label is keep_h(DISABLE_FLATTEN);
 150     attribute keep_hierarchy of decode2_0 : label is keep_h(DISABLE_FLATTEN);
 151     attribute keep_hierarchy of register_file_0 : label is keep_h(DISABLE_FLATTEN);
 152     attribute keep_hierarchy of cr_file_0 : label is keep_h(DISABLE_FLATTEN);
 153     attribute keep_hierarchy of execute1_0 : label is keep_h(DISABLE_FLATTEN);
 154     attribute keep_hierarchy of loadstore1_0 : label is keep_h(DISABLE_FLATTEN);
 155     attribute keep_hierarchy of mmu_0 : label is keep_h(DISABLE_FLATTEN);
 156     attribute keep_hierarchy of dcache_0 : label is keep_h(DISABLE_FLATTEN);
 157     attribute keep_hierarchy of writeback_0 : label is keep_h(DISABLE_FLATTEN);
 158     attribute keep_hierarchy of debug_0 : label is keep_h(DISABLE_FLATTEN);
 159 begin
 160
 161     core_rst <= dbg_core_rst or rst;
 162
 163     resets: process(clk)
 164     begin
 165         if rising_edge(clk) then
 166             rst_fetch1  <= core_rst;
 167             rst_fetch2  <= core_rst;
 168             rst_icache  <= core_rst;
 169             rst_dcache  <= core_rst;
 170             rst_dec1    <= core_rst;
 171             rst_dec2    <= core_rst;
 172             rst_ex1     <= core_rst;
 173             rst_ls1     <= core_rst;
 174             rst_dbg     <= rst;
 175             alt_reset_d <= alt_reset;
 176         end if;
 177     end process;
 178
 179     fetch1_0: entity work.fetch1
 180         generic map (
 181             RESET_ADDRESS => (others => '0'),
 182             ALT_RESET_ADDRESS => ALT_RESET_ADDRESS
 183             )
 184         port map (
 185             clk => clk,
 186             rst => rst_fetch1,
 187             alt_reset_in => alt_reset_d,
 188             stall_in => fetch1_stall_in,
 189             flush_in => fetch1_flush,
 190             stop_in => dbg_core_stop,
 191             d_in => decode1_to_fetch1,
 192             e_in => execute1_to_fetch1,
 193             i_out => fetch1_to_icache,
 194             log_out => log_data(42 downto 0)
 195             );
 196
 197     fetch1_stall_in <= icache_stall_out or decode1_busy;
 198     fetch1_flush <= flush or decode1_flush;
 199
 200     icache_0: entity work.icache
 201         generic map(
 202             SIM => SIM,
 203             LINE_SIZE => 64,
 204             NUM_LINES => 64,
 205             NUM_WAYS => 2,
 206             LOG_LENGTH => LOG_LENGTH
 207             )
 208         port map(
 209             clk => clk,
 210             rst => rst_icache,
 211             i_in => fetch1_to_icache,
 212             i_out => icache_to_decode1,
 213             m_in => mmu_to_icache,
 214             flush_in => fetch1_flush,
 215             inval_in => dbg_icache_rst or ex1_icache_inval,
 216             stall_in => icache_stall_in,
 217             stall_out => icache_stall_out,
 218             wishbone_out => wishbone_insn_out,
 219             wishbone_in => wishbone_insn_in,
 220             log_out => log_data(96 downto 43)
 221             );
 222
 223     icache_stall_in <= decode1_busy;
 224
 225     decode1_0: entity work.decode1
 226         generic map(
 227             LOG_LENGTH => LOG_LENGTH
 228             )
 229         port map (
 230             clk => clk,
 231             rst => rst_dec1,
 232             stall_in => decode1_stall_in,
 233             flush_in => flush,
 234             flush_out => decode1_flush,
 235             busy_out => decode1_busy,
 236             f_in => icache_to_decode1,
 237             d_out => decode1_to_decode2,
 238             f_out => decode1_to_fetch1,
 239             log_out => log_data(109 downto 97)
 240             );
 241
 242     decode1_stall_in <= decode2_stall_out;
 243
 244     decode2_0: entity work.decode2
 245         generic map (
 246             EX1_BYPASS => EX1_BYPASS,
 247             LOG_LENGTH => LOG_LENGTH
 248             )
 249         port map (
 250             clk => clk,
 251             rst => rst_dec2,
 252             busy_in => decode2_busy_in,
 253             stall_out => decode2_stall_out,
 254             flush_in => flush,
 255             complete_in => complete,
 256             stopped_out => dbg_core_is_stopped,
 257             d_in => decode1_to_decode2,
 258             e_out => decode2_to_execute1,
 259             r_in => register_file_to_decode2,
 260             r_out => decode2_to_register_file,
 261             c_in => cr_file_to_decode2,
 262             c_out => decode2_to_cr_file,
 263             log_out => log_data(119 downto 110)
 264             );
 265     decode2_busy_in <= ex1_busy_out;
 266
 267     register_file_0: entity work.register_file
 268         generic map (
 269             SIM => SIM,
 270             LOG_LENGTH => LOG_LENGTH
 271             )
 272         port map (
 273             clk => clk,
 274             d_in => decode2_to_register_file,
 275             d_out => register_file_to_decode2,
 276             w_in => writeback_to_register_file,
 277             dbg_gpr_req => dbg_gpr_req,
 278             dbg_gpr_ack => dbg_gpr_ack,
 279             dbg_gpr_addr => dbg_gpr_addr,
 280             dbg_gpr_data => dbg_gpr_data,
 281             sim_dump => terminate,
 282             sim_dump_done => sim_cr_dump,
 283             log_out => log_data(255 downto 185)
 284             );
 285
 286     cr_file_0: entity work.cr_file
 287         generic map (
 288             SIM => SIM,
 289             LOG_LENGTH => LOG_LENGTH
 290             )
 291         port map (
 292             clk => clk,
 293             d_in => decode2_to_cr_file,
 294             d_out => cr_file_to_decode2,
 295             w_in => writeback_to_cr_file,
 296             sim_dump => sim_cr_dump,
 297             log_out => log_data(184 downto 172)
 298             );
 299
 300     execute1_0: entity work.execute1
 301         generic map (
 302             EX1_BYPASS => EX1_BYPASS,
 303             LOG_LENGTH => LOG_LENGTH
 304             )
 305         port map (
 306             clk => clk,
 307             rst => rst_ex1,
 308             flush_out => flush,
 309             busy_out => ex1_busy_out,
 310             e_in => decode2_to_execute1,
 311             l_in => loadstore1_to_execute1,
 312             ext_irq_in => ext_irq,
 313             l_out => execute1_to_loadstore1,
 314             f_out => execute1_to_fetch1,
 315             e_out => execute1_to_writeback,
 316             icache_inval => ex1_icache_inval,
 317             dbg_msr_out => msr,
 318             terminate_out => terminate,
 319             log_out => log_data(134 downto 120),
 320             log_rd_addr => log_rd_addr,
 321             log_rd_data => log_rd_data,
 322             log_wr_addr => log_wr_addr
 323             );
 324
 325     loadstore1_0: entity work.loadstore1
 326         generic map (
 327             LOG_LENGTH => LOG_LENGTH
 328             )
 329         port map (
 330             clk => clk,
 331             rst => rst_ls1,
 332             l_in => execute1_to_loadstore1,
 333             e_out => loadstore1_to_execute1,
 334             l_out => loadstore1_to_writeback,
 335             d_out => loadstore1_to_dcache,
 336             d_in => dcache_to_loadstore1,
 337             m_out => loadstore1_to_mmu,
 338             m_in => mmu_to_loadstore1,
 339             dc_stall => dcache_stall_out,
 340             log_out => log_data(149 downto 140)
 341             );
 342
 343     mmu_0: entity work.mmu
 344         port map (
 345             clk => clk,
 346             rst => core_rst,
 347             l_in => loadstore1_to_mmu,
 348             l_out => mmu_to_loadstore1,
 349             d_out => mmu_to_dcache,
 350             d_in => dcache_to_mmu,
 351             i_out => mmu_to_icache
 352             );
 353
 354     dcache_0: entity work.dcache
 355         generic map(
 356             LINE_SIZE => 64,
 357             NUM_LINES => 64,
 358             NUM_WAYS => 2,
 359             LOG_LENGTH => LOG_LENGTH
 360             )
 361         port map (
 362             clk => clk,
 363             rst => rst_dcache,
 364             d_in => loadstore1_to_dcache,
 365             d_out => dcache_to_loadstore1,
 366             m_in => mmu_to_dcache,
 367             m_out => dcache_to_mmu,
 368             stall_out => dcache_stall_out,
 369             wishbone_in => wishbone_data_in,
 370             wishbone_out => wishbone_data_out,
 371             log_out => log_data(171 downto 152)
 372             );
 373
 374     writeback_0: entity work.writeback
 375         port map (
 376             clk => clk,
 377             e_in => execute1_to_writeback,
 378             l_in => loadstore1_to_writeback,
 379             w_out => writeback_to_register_file,
 380             c_out => writeback_to_cr_file,
 381             complete_out => complete
 382             );
 383
 384     log_data(151 downto 150) <= "00";
 385     log_data(139 downto 135) <= "00000";
 386
 387     debug_0: entity work.core_debug
 388         generic map (
 389             LOG_LENGTH => LOG_LENGTH
 390             )
 391         port map (
 392             clk => clk,
 393             rst => rst_dbg,
 394             dmi_addr => dmi_addr,
 395             dmi_din => dmi_din,
 396             dmi_dout => dmi_dout,
 397             dmi_req => dmi_req,
 398             dmi_wr => dmi_wr,
 399             dmi_ack => dmi_ack,
 400             core_stop => dbg_core_stop,
 401             core_rst => dbg_core_rst,
 402             icache_rst => dbg_icache_rst,
 403             terminate => terminate,
 404             core_stopped => dbg_core_is_stopped,
 405             nia => fetch1_to_icache.nia,
 406             msr => msr,
 407             dbg_gpr_req => dbg_gpr_req,
 408             dbg_gpr_ack => dbg_gpr_ack,
 409             dbg_gpr_addr => dbg_gpr_addr,
 410             dbg_gpr_data => dbg_gpr_data,
 411             log_data => log_data,
 412             log_read_addr => log_rd_addr,
 413             log_read_data => log_rd_data,
 414             log_write_addr => log_wr_addr,
 415             terminated_out => terminated_out
 416             );
 417
 418 end behave;